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asm as "memory barrier"
- From: Paul Koning <pkoning at equallogic dot com>
- To: gcc at gcc dot gnu dot org
- Date: Wed, 23 Apr 2003 15:55:57 -0400
- Subject: asm as "memory barrier"
I have a two-CPU setup with some shared data structures. One CPU is
"active", the other is "standby". The active is the source of a lot
of data, which the standby is accepting.
For things to work right, I need to make sure that there's a partial
order of the writes that the standby CPU sees.
The obvious answer is to sprinkle "volatile" everywhere, and indeed
that's what we currently do. But that's very much overkill, because
we don't need every read and write of the variables to be a memory
reference, and we don't need total order, only partial order.
What I really need is the GCC analog of a "memory barrier", i.e., a
marker in the source code that says "make sure that all the stores
that were coded before this point are seen before any of the stores
coded after this point".
The obvious answer is:
asm volatile ("" : : : "memory");
and indeed that appears to do the job. It forces the code generator
to emit all the stores for data that's currently in registers but
needs to go to variables. That's what I want.
But it also (as documented) causes the compiler to assume that memory
has changed since then, i.e., anything it loaded before is no longer
valid. That's NOT what I want.
I also tried:
asm volatile ("");
That did what I wanted -- forces the stores but doesn't invalidate the
registers (in gcc 3.0.1 for mips at least). The trouble is that I
don't see any documentation that tells me this, so I am loath to rely
on this property.
Is this indeed something I can count on? (I.e., should this be
documented?) If not, any other suggestions?
BTW, I don't need to generate any actual machine code here; the
machine I'm using has the right ordering properties in the hardware,
so, for example,
asm volatile ("sync");