Re: RFC: new rtl vec_set_unit/vec_get_unit

[Aldy Hernandez <aldyh at redhat dot com>]

Quoting the context...

> > It was suggested that we add new RTL code to deal with this, but the
> > exact semantics had not been proposed.  I'm taking this up again, and
> > here is the proposed syntax:
> >
> > 	(vec_set_unit:SI (reg:V2SI r9) 1 (reg:SI r5))
> >
> > and
> >
> > 	(set (reg:SI r88) (vec_get_unit:SI (reg:V2SI r9) 1))
> >
> > Then, the expanders:
> >
> > (define_expand "vec_set_unitv2si"
> > 	(set (match_operand:V2SI 0)
> > 	     (vec_set_unit:V2SI (match_operand:V2SI 1)
> > 				(match_operand 2 immediate)
> > 				(match_operand:SI 3)))
> >
> > and...
> >
> > (define_expand "vec_get_unitv2si"
> >   [(set (match_operand:SI 0)
> > 	    (vec_get_unit:SI (match_operand:V2SI 1)
> > 						 (match_operand:SI 2)))]
> >
> > I think it's all pretty clear.  If no one objects as to the syntax,
> > I'll start hacking away.
>
> This is still something I would like to look into.  The expanders to
> get/set pariticular fields of the vector looks like obvious sollution.

"Look into", as in you're volunteering?  I'd gladly tackle other 
things.  Let me know.

> However the problem is that the code generated for SSE would be ugly,
> especially when taking into account V16QImode where to access 
> paritcular
> mode number of rotations on different temporaries needs to be made.
>
> Most of the time we need to get/set all the fields of vector at once 
> (to
> simulate vector operation) so perhaps we should have both.
> We probably need both mechanizms as in some cases it is deifnitly
> desirable to access particular fields of the vector.

Example?

> Also vec_set_unit/vec_get_unit can be expanded into
> vec_select/vec_duplicate operations so there is probably no need to
> invent the RTL construct for that, we only need the named patterns.

Ok I see you're using vec_select in the x86 backend to get to a 
particular element.  This is definitely better than my approach, but I 
suggest we document it.

How does this look for extraction?:

(set (match_operand:SI 99)
     (vec_select:SI (match_operand:V4SI 3))

However... how do you suggest we do the set operation, as in setting an 
element of vector to a particular value. ??  You can't use vec_select 
as a left hand value without major surgery, pretty much every place we 
handle zero_extract, sign_extract, subreg, and strict_low_part.

For the set, I was suggesting completely different rtl, ala:

> 	(vec_set_unit:SI (reg:V2SI r9) 1 (reg:SI r5))
>
> Then, the expanders:
>
> (define_expand "vec_set_unitv2si"
> 	(set (match_operand:V2SI 0)
> 	     (vec_set_unit:V2SI (match_operand:V2SI 1)
> 				(match_operand 2 immediate)
> 				(match_operand:SI 3)))

Aldy