Re: Words endian is different in registers than in memory

[Andrew Haley <aph at redhat dot com>]

adland at stud dot ntnu dot no writes:
 > Your answer led to a new question, using an example to show it:
 > 
 > load    r0, r6
 > 
 > This instruction is loading a 64-bit value from an address stored in r6 to
 > register r1:r0. Internally the registers are swaped, meaning that the
 > first operand, r0, is refered to as 1 (REG:SI 1 r0). GCC is using
 > consecutive register pairs, that would be 2 (REG:SI 2 r3). This means that
 > GCC belives that the 64-bit value is stored in r3:r0. How can I tell GCC
 > to use register 0 (REG:SI 0 r1) instead?

We already know that the registers are oppositely endian to memory.
I'm assuming that a two word load does the right thing, and so the low
address word in memory ends up in the higher number register and vice
versa.  I'm also assuming that the register mentioned in a 64-bit load
instruction is the low numbered of a pair.

So, when gcc does (set (reg:DI 0 r1) (mem:DI (reg:SI 7 r6)))
I guess you'll want to output

load	r0, r6

instead of

load	r1, r6

so you'll have to detect a 64-bit operation and massage the output
operands specially.  Whenever a register being addressed is a 64-bit
pair tou have to emit (register# xor 1).

Andrew.

 > Quoting Andrew Haley <aph at redhat dot com>:
 > 
 > > =?ISO-8859-1?Q?Anders=5F=C5dland?= writes:
 > >  > Hi
 > >  > 
 > >  > I am porting GCC to a new architecture and have one problem when
 > > defining
 > >  > WORDS_BIG_ENDIAN because "GCC fundamentally assumes that the order
 > > of
 > >  > words in memory is the same as the order in registers." In my case
 > > it
 > >  > should be defined as 0 when working with memory and 1 when working
 > > with
 > >  > registers.
 > > 
 > > I think you're saying that Register 0 is the high word of R0:R1, but
 > > memory has little endian words, with the low word first, so you want
 > > to store R0 in a higher address than R1.  Could you swap the register
 > > names so that gcc's internal register zero maps on to real hardware
 > > register 1, and vice versa?  You'd have something like REG:SI 0 r1 and
 > > REG:SI 1 r0.
 > > 
 > > Andrew.
 > > 
 > 
 >