Hi,
On Thu, Feb 27, 2003 at 02:04:14AM +0100, Zdenek Dvorak wrote:
The "old" loop optimizer does BIV-to-GIV flattening which is
important on
processors without double-register addressing modes such as the SH,
MIPS16, Thumb, and a few others.
Does the new loop optimizer support this feature?
no; as I said, anything related to iv's is problem.
Right now I'm working on a pass that enrich the SSA representation
by the IV functions information. IVs are represented by chains of
recurences as described in: