Re: instruction scheduler and passing arguments in registers

[Vladimir Makarov <vmakarov at redhat dot com>]

Jonah Graham wrote:
> 
> Hello,
> 
> I am working on a port of GCC using the DFA scheduler. The processor
> ABI passes its first two arguments in registers. That causes a problem,
> the lifetime of the argument register get increased unnecessarily when
> a simple value is moved to it (eventually leading to a spill failure).
> 
> For example:
> 
> void simple_a (int, int);
> 
> void simple_b (int x, int y)
> {
>    increment x, multiply it by y, do a bunch of other
>    more stuff....
>    simple_a (2, x);
> }
> 
> will create RTL roughly like:
> 
>    (insn 1 (set x (add x y)))
>    (insn 2 (set x (mult x y)))
>    ...
>    (insn 45 (set r0 (const_int 2)))
>    (insn 46 (set r1 x))
>    (call_insn 47 (call simple_a))
> 
> When the scheduler runs it moves insn 45 to near the top. (It is actually
> in the initial ready list for the basic block). That causes r0 to be in use
> throughout the basic block (instead of for just a couple of insns before the
> call). Because it is used throughout, it gets marked as such and reload cannot
> use it. The final result is I have spill failures, something I did not use to
> have before I started using the instruction scheduler.
> 
> Any suggestions as to the cause or a resolution would be highly appreciated.
> 
>

The problem could be solved in a lot of ways.  The most right solution
is to form schedule group as now post call insn groups (see
in_post_call_group_p) are formed.

There are other solutions too.  The first one is not to use insn
scheduling before the register allocation (it is ok if the processor has
small number of registers).  Another solution is to use hook
first_cycle_multipass_dfa_lookahead_guard (or switch off first cycle
multipass scheduling) and hooks to reorder ready queue.

Vlad