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Re: ARM interrupts
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Nick Clifton <nickc at redhat dot com>
- Cc: Eric de Jong <eric2work at yahoo dot com>, gcc at gnu dot org, ericdejong at gmx dot net, Richard dot Earnshaw at arm dot com
- Date: Thu, 23 Jan 2003 12:18:32 +0000
- Subject: Re: ARM interrupts
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
> #ifdef ATPCS_STACK_ALIGN
> bic sp, sp, #7 /* If stack alignment required. */
> #endif
Thinking about this some more, this isn't needed with the current level of
IRQ support that we provide. We don't allow nested interrupts (we don't
preserve the SPSR), so we can assume that the appropriate interrupt stack
is correctly aligned on entry. At most we need to add a normal stack
adjustment.
R.