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Re: An unusual Performance approach using Synthetic registers
- From: <tm_gccmail at mail dot kloo dot net>
- To: Marcel Cox <marcel_cox at hotmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Tue, 7 Jan 2003 15:36:04 -0800 (PST)
- Subject: Re: An unusual Performance approach using Synthetic registers
On Tue, 7 Jan 2003 tm_gccmail@mail.kloo.net wrote:
> On Tue, 7 Jan 2003, Marcel Cox wrote:
> (stuff deleted for brevity)
> ...
> > I think the speed gain is achieved for the following reasons:
> >
> > 1) The most active variables are kept close together in memory. They only
> > occupy one or a few cache lines. Normally, one would expect the stack frame
> > to always be in L1 cache. However especially when traversing data structures
> > that are bigger than L1 cache, you can expect the cache lines holding the
> > stack frame to be regularly be replaced by data, and having fewer cache
> > lines to reload for local variables will certainly give a speed advantage.
>
> The stack reordering pass posted by Sanjiv Gupta can do this.
> This was posted about a few days ago in gcc-patches.
>
> What you're describing is actually bad on the Pentium, and probably
> subsequent implementations as well.
>
> The Pentium can dual-issue loads as long as they reference separate cache
> ways. So, manually sorting the stack so contiguous accesses are localized
> increases the probability of the loads accessing the same cache way, thus
> decreasing the probability of single-issuing.
That should read "decreasing the probability of dual-issuing" - apologies.
Toshi