Re: An unusual Performance approach using Synthetic registers

[Michael S. Zick <mszick at goquest dot com>]

On Tuesday 07 January 2003 06:47 am, Robert Dewar wrote:
> I had thought that these instructions were only available on recent chips,
> so if they are used you have to be careful about back compatibility.
>
Good advice;
Andy, you mentioned your machine was a "Pentium" (without any
qualifications) so your machine doesn't have prefetch instructions.

Momchil Velikov <velco at fadata dot bg> gave a nice list in his post.

The exchange (xchg) instruction was included in the original 80386.
It also issued a "bus lock" signal from the chip but as time passed,
problems where found with its timing and its use for atomically handling
symiphores was replaced with new instructions for that purpose.

It has always done its register <-> memory thing correctly.

Also, your "Pentium" (without any qualifications) does not have the
"out of order execution, with register renaming, in multiple execution
units" grown into its silcon.  Just ignore us on that subject.

The hard way to learn about all of this is to start at this link:
<http://www.intel.com/support/processors/index.htm>

Pick your processor, on that processor's page will be a link to
manuals - including more than you ever wanted to know.
Most of the manuals discuss earlier versions of the chip in
contrast to the subject chip.

A good mid-point in the product line would be:
<http://www.intel.com/design/pentiumii/manuals/245127.htm>

Which I believe Robert was refering too.

The easy way is to just keep on asking the list, some of us
have been writing Intel-ASM since the I-4004 hit the 
street. (Myself included.)

Mike