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Re: An unusual Performance approach using Synthetic registers
- From: Michael S. Zick <mszick at goquest dot com>
- To: dewar at gnat dot com (Robert Dewar),dewar at gnat dot com,lord at emf dot net
- Cc: gcc at gcc dot gnu dot org,ja_walker at earthlink dot net
- Date: Sun, 5 Jan 2003 10:25:12 -0600
- Subject: Re: An unusual Performance approach using Synthetic registers
- References: <20030105140515.3119CF2DD2@nile.gnat.com>
On Sunday 05 January 2003 08:05 am, Robert Dewar wrote:
> > Bah. I missed that (misread while skimming, actually). Maybe his
> > implementation approach is bogus after all. Why not use the FP, if
> > it's there, or SP when FP is omitted.
>
> well indeed FP makes more sense, and that's why the discussoin lead there
>
> > But it can also improve both locality and the temporally proximate
> > re-use of memory locations.
>
> That's really not an issue for scalars. L1 caches are small but not that
> small. once again, empirically most references to local stack frames are
> in cache anyway, so there's really not much to improve here.
>
> > ja_walker is right: it's a worthwhile emperical question
>
Agreed.
Further consider: Any line of investigation that provides leads
to improvements in cache utilization is worthwhile.
Example, my several year out-of-date system:
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 512K
Both running at core clock speed.
(Times two of them {SMP})
Ignoring the fact that they aren't linearly addressable memory;
going by size alone...
That is enough memory to run PC-DOS in along with a few
memory resident programs and a respectable sized application,
such as a spreadsheet program and never touch main memory.
Mike