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Re: divmod with -O3
- From: Pierre Mallard <pierremallard at yahoo dot fr>
- To: Richard Henderson <rth at redhat dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 20 Nov 2002 16:04:59 +0100 (CET)
- Subject: Re: divmod with -O3
May I ? ...
Ok for unsigned udivmodqi4 it works fine but seems
that the signed divmodqi4 is never taken then ... Gcc
prefer to get divmodhi4... maybe u know sthg about it
?
(define_insn_and_split ""
[(set (match_operand:QI 0 "nonimmediate_operand"
"=rm")
(truncate:QI (div:HI (match_operand:HI 3
"register_operand" "r")
(sign_extend:HI (match_operand:QI 4
"register_operand" "r")))))
(set (match_operand:QI 1 "nonimmediate_operand"
"=rm")
(truncate:QI (mod:HI (sign_extend:HI (match_dup 3))
(sign_extend:HI (match_dup 4)))))
(clobber (match_scratch:HI 2 "=r"))]
""
"#"
"reload_completed"
[(set (match_dup 2) (unspec:HI [(match_dup 3)
(match_dup 4)] 5))
(set (match_dup 0) (match_dup 5))
(set (match_dup 1) (match_dup 6))]
"{
operands[5] = gen_lowpart (QImode, operands[2]);
operands[6] = gen_highpart (QImode, operands[2]);
}")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:HI 1 "register_operand"
"r")
(sign_extend:HI (match_operand:QI 2
"register_operand" "r"))]5))]
""
"divss %0,%1,%2"
[(set_attr "length" "1")
(set_attr "cc" "none")])
(It's the same if instead of sign_extend there's only
QI register)
DIVMODHI4 :
(define_expand "divmodhi4"
[(parallel[(set (match_operand:HI 0
"general_operand" "")
(div:HI (match_operand:HI 1 "general_operand"
"")
(match_operand:HI 2
"general_operand" "")))
(set (match_operand:HI 3 "general_operand"
"")(mod:HI (match_dup 1) (match_dup 2)))])]
""
"{
emit_move_insn (gen_rtx_REG (HImode, 24),
operands[1]);
emit_move_insn (gen_rtx_REG (HImode, 26),
operands[2]);
emit_library_call_value(gen_rtx_SYMBOL_REF(Pmode,\"__divmodhi4\"),
gen_rtx_REG (SImode, 24) , 0, SImode, 2 , gen_rtx_REG
(HImode, 24) , HImode , gen_rtx_REG (HImode, 26) ,
HImode);
emit_move_insn (operands[3], gen_rtx_REG
(HImode, 24));
emit_move_insn (operands[0], gen_rtx_REG
(HImode, 26));
DONE;
}")
Regards
Pierre Mallard
--- Richard Henderson <rth@redhat.com> a écrit : > On
Tue, Nov 19, 2002 at 05:28:54PM +0100, Pierre
> Mallard wrote:
> > res = gen_reg_rtx(HImode);
> > emit_insn (gen_rtx_PARALLEL(VOIDmode, gen_rtvec
> (2,
> > gen_rtx_SET
> >
>
(VOIDmode,gen_rtx_SUBREG(QImode,res,0),gen_rtx_UDIV(QImode,operands[1],operands[2])),
> > gen_rtx_SET
> >
>
(VOIDmode,gen_rtx_SUBREG(QImode,res,1),gen_rtx_UMOD(QImode,operands[1],operands[2]))
> > )));
>
> Your problem is going to be that you require two
> consecutive registers,
> but did not express this so that rename_registers
> could honor it. Yes?
>
> You're going to need to represent this some other
> way.
>
> One option is to do
>
> (define_insn_and_split ""
> [(set (match_operand:QI 0 "nonimmediate_operand"
> "=rm")
> (udiv:QI (match_operand:QI 3 "register_operand"
> "r")
> (match_operand:QI 4 "register_operand" "r")))
> (set (match_operand:QI 1 "nonimmediate_operand"
> "=rm")
> (umod:QI (match_dup 3) (match_dup 4)))
> (clobber (match_scratch:HI 2 "=r"))]
> ""
> "#"
> "reload_completed"
> [(set (match_dup 2)
> (unspec:HI [(match_dup 3) (match_dup 4)]
> UNSPEC_DIVMOD))
> (set (match_dup 0) (match_dup 5))
> (set (match_dup 1) (match_dup 6))]
> {
> operands[5] = gen_lowpart (QImode, operands[2]);
> operands[6] = gen_highpart (QImode, operands[2]);
> })
>
> (define_insn ""
> [(set (match_operand:HI 0 "register_operand" "=r")
> (unspec:HI [(match_operand:QI 1 "register_operand"
> "r")
> (match_operand:QI 2 "register_operand" "r")]
> UNSPEC_DIVMOD))]
> ""
> "...")
>
>
> r~
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