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Re: Status of SSE builtins
Richard Henderson wrote:
>
> On Wed, Oct 30, 2002 at 10:41:40PM +0100, Jan Hubicka wrote:
> > We generate instruction dealing with elements of the vector using
> > subregs, like (subreg:HI (reg:V4HI) 2) is expected to access and modify
> > only the second field of the vector. However the subregs gneerally
> > clobber whole word in GCC and are not allowed in such general forms.
>
> Yes, I was talking with Aldy about this recently. He has the
> same problem for Motorola BookE vectors.
>
> I think the proper solution is to have named patterns in the md file
> that the rtl expander will use to satisfy these insertions and extractions.
> If the named patterns do not exist, or FAIL, then we fall back to a
> combination of subreg and insert/extract bitfield.
We could also have a target macro that controls the word size (i.e.
hard register size) being assumed for an access of a subparty in one
mode of an entity in another mode. For SSE2 targets, you would give the
size of the SSE2 registers.
This value can than be used instead of UNITS_PER_WORD in the generic simd
code - and elsewhere if appropriate - to control wheather to use subregs or
extract_bit_field / store_bit_field.
This would make the target code a lot simpler than having to write expanders
for every extraction. Of course, that is assuming that extract_bit_field
will work OK.
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