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Incorrect DFA scheduling of inline assembly
- From: Dan Towner <dant at picochip dot com>
- To: gcc at gcc dot gnu dot org
- Date: Thu, 31 Oct 2002 09:52:28 +0000
- Subject: Incorrect DFA scheduling of inline assembly
- Organization: picoChip Designs Ltd.
Hi all,
I am using the DFA scheduler for a 16-bit VLIW processor port. Some of
my code contains inline assembler, and it appears that the scheduler is
not allocating any resources to those instructions. This means that the
inline assembly instructions are being incorrectly scheduled alongside
other instructions:
;; ======================================================
;; -- basic block 7 from 62 to 147 -- after reload
;; ======================================================
;; 0--> 62 R6=R1 :slot0|slot1
;; 1--> 64 R5=asm_operands :nothing
;; 1--> 89 R6=R4|R3 :slot0|slot1
;; Ready list (final):
;; total time = 1
;; new head = 62
;; new tail = 89
Notice that the asm_operands instructions, and the OR operation have
both been scheduled into cycle 1, even though this should never happen -
the asm instruction could use any number of VLIW slots.
I would have thought that inline assembly instructions would have had
the `unknown' attribute (i.e., the default for my attribute `type'),
which would have meant that they used all the VLIW slots. Instead, they
are somehow being scheduled so that they appear not to require any slots
at all!
Any ideas?
Thanks,
Dan.
=============================================================================
Daniel Towner
picoChip Designs Ltd., Riverside Buildings, 108, Walcot Street, BATH,
BA1 5BG
dant@picochip.com
07786 702589