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Status of SSE builtins
- From: Joern Rennecke <joern dot rennecke at superh dot com>
- To: Jan Hubicka <jh at suse dot cz>
- Cc: gcc at gcc dot gnu dot org, rth at cygnus dot com, bernds at redhat dot com, aj at suse dot de
- Date: Wed, 30 Oct 2002 21:22:34 +0000
- Subject: Status of SSE builtins
- Organization: SuperH UK Ltd.
> 4) Missaligned load/store buitins
> The use of missaligned loads/stores results in GCC eventually
> keeping the values in register and producing "internal" move for it
> resulting in trap. I am not sure how to model this properly.
Make the misaligned load explicit as a special operation.
You can use insv / extv in your pattern, or use two memory references
that are explicitly aligned upwards / downwards and put the pieces
together with arithmetic.
> 5) generic SIMD support is quite broken right now as SSE does not
> allow scalar opration on elements of vectors registers, like Sparc and
> other sane instruction sets most probably do. I am not quite sure how
> to get arround here and I also think the RTL produced is invalid when
> dealing with vectors containing elements smaller than word size.
Can you give an example?
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