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Re: [DFA]: Scheduling for zSeries and S/390
- From: "Hartmut Penner" <HPENNER at de dot ibm dot com>
- To: Vladimir Makarov <vmakarov at redhat dot com>
- Cc: gcc at gcc dot gnu dot org, Ulrich Weigand <Ulrich dot Weigand at de dot ibm dot com>, vmakarov at toronto dot redhat dot com
- Date: Tue, 1 Oct 2002 08:57:04 +0200
- Subject: Re: [DFA]: Scheduling for zSeries and S/390
Vlad wrote:
> I'd name your variant of description as a structural one because it is
>close to processor documentation. You could also use what I name a
>behavioural description. Such description does not follow processor
>description but correctly describes all pipeline hazards. For example,
>you could remove dec, agen, c1, and c2 and still get the same
>automaton. Usage of structural or behavioral description is a matter of
>taste.
I guess, I'll change it to behavioral description.
One more question I have, how could I model the behavior of the
Load address instruction, which has a special bypass to agen.
The behavior is as follow:
cycle 0 1 2 3 4 5 6 7
LA . L
LA x . L
LA x x . L
LA x x x . L
LA x x x x L
where LA sets address register used in L, . is a pipeline stall and x is
any unrelated instruction.
That means, the LA is a 2 cycle instruction only in case of less than 4
instruction between, 1 cycle
in all other cases.
regards,
Hartmut