Re: Single Element Vectors

[Kumar Gala <kumar dot gala at motorola dot com>]

On Thursday, September 12, 2002, at 04:14  PM, Richard Henderson wrote:

> On Thu, Sep 12, 2002 at 10:36:29AM +0100, Nick Clifton wrote:
> >   We have a request from a customer to implement support for a single
> >   element vectors in gcc for one of their processors.  Their ABI
> >   requires that vectors are handled differently from ordinary types,
> >   and it includes a single element, 64-bit vector which GCC would
> >   normally consider to be exactly equivalent to a long long.
> Oh heavens.
>
> >   If so, they would like to know why single element vectors should not
> >   be supported.
> What possible usefulness could they have?  Semantically they
> are exactly the same as a scalar.  To my way of thinking,
> that they want this shows that they are confused and making
> distinctions that don't make sense.
>
> > What ramifications does it have and what would supporting them break ?
> Nothing but cleanliness of the compiler.
I think there are cases in which a single element vector data type are 
required.  While from a logical point of view single element vectors 
are the same as scalars, however the compiler needs to have a way to 
distinguish the fact that its a scalar from a vector.

Most vector instruction sets that I am aware of (AltiVec, SPE, SSE) use 
separate (or merged) register files to handle the vector instructions.  
This has meant that ABI's have defined new calling conventions for 
vector data types to pass arguments in vector registers.  How is the 
compiler suppose to comply with the ABI if it can not tell the 
difference between a single element vector and scalar.

For example, if we have a vector length of 64-bits.  In the PPC ABI a 
'long long' is passed in two general purpose registers.  A vector data 
type is passed in a single vector register.  If single element vectors 
are treated as scalars how will the compiler do the right thing here?

In the SPE ISA (see http://e-www.motorola.com/collateral/EREF_CH.html) 
there are multiply-accumulate instructions which produce single 64-bit 
results in the vector registers.  If I have an algorithm which requires 
use of one of these instructions what is the user suppose to do?  How 
do they get the compiler to take advantage of the feature?

If we treat this case as a scalar, then I would expect the compiler to 
convert the vector used up to that point to a scalar, do the 
computation in scalar form, and then possible return it to a vector to 
continue the algorithm.  This appears hurt performance by not taking 
advantage of support that exists in the hardware.

I have worked with Aldy on some of this and am more then happy to try 
to take input to solve my problem (while still taking advantage of the 
instruction set we have created).


- kumar