Baffled by secondary reload

[Paul Koning <pkoning at equallogic dot com>]

Gentlepeople,

I've read and re-read the docs, and tried lots of stuff, and I'm still
baffled.

Consider a platform (PDP-11, actually) where float registers come in
two flavors:

    a. 0..3, valid anywhere
    b. 4 and 5, can appear in two-operand instructions only when the
       other operand is float register 0..3.

So for examp, this isn't valid:
      (set (reg:DF ac4) (reg:DF ac5))

The challenge is to keep the compiler from generating this.

I created two register class letters ('a' and 'b' as above), and
defined the constraints on the movdf pattern so source and dest both
'b' is not accepted.

I also defined PREFERRED_RELOAD_CLASS and
PREFERRED_OUTPUT_RELOAD_CLASS to say that loading to/from 'b' wants to
use 'a' instead.

Next, I defined SECONDARY_RELOAD_CLASS to say that a move between 'b'
and anything other than 'a' requires a secondary 'a'.

Finally, I defined reload_indf and reload_outdf patterns, the former
with operand 0 constraint "=b" and the latter with operand 1
constraint "b".

So as far as I can see I have done what the manual calls for.

Unfortunately, my compiles still abort, with reload1 complaining that
an insn doesn't satisfy the constraints.  The insn in question looks
like the example I gave above of something that's not permitted.

So the question is: what did I miss?  Why doesn't
SECONDARY_RELOAD_CLASS tell the register allocator not to allocate
registers the way it did?  Or why didn't reload fix the damage?

Where do I look to trace what's going wrong?

      paul