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Re: Reasonable L1 cache miss rate for gcc
- From: Daniel Jacobowitz <drow at false dot org>
- To: Daniel Berlin <dberlin at dberlin dot org>
- Cc: gcc at gcc dot gnu dot org
- Date: Sun, 11 Aug 2002 11:20:45 -0400
- Subject: Re: Reasonable L1 cache miss rate for gcc
- References: <Pine.LNX.4.44.0208110037020.4997-100000@dberlin.org>
On Sun, Aug 11, 2002 at 01:12:39AM -0400, Daniel Berlin wrote:
> What is a reasonable L1 cache miss rate (for memory loads
> only not instructions) is for a P4 running GCC?
>
> I have the exact figures, but without some idea of what reasonable would
> be, i have no idea how *bad* it is.
>
> Percentage wise, it's a 14-25% miss rate (depending on input).
>
> Of course, I really want to know about L2's, but the file describing all
> the available p4 pmcs says:
> Sigh.
>
> Someone with a PIII should be able to get oprofile to give us some l2
> numbers.
Assuming that I actually figured out what these numbers mean...
I remade insn-*.o in a gcc HEAD build with two compilers (no
optimization):
DATA_MEM_REFS L2_LINES_IN L2 Miss %
GCC 2.95.3 cc1 4.32e9 3.23e7 0.7%
GCC 3.1.1 cc1 7.0265e9 6.3e7 0.8%
Something tells me I've got the wrong numbers, though... those look far
too low. If someone cares to enlighten me on the right counters to
use, I'll be more thorough.
--
Daniel Jacobowitz
MontaVista Software Debian GNU/Linux Developer