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Re: Vector modes under hppa64-hpu


  	  else
  	    t = simplify_gen_subreg (submode, target, mode, i * subsize);
! 	  if (CONSTANT_P (op0) || GET_CODE (op0) == REG)
  	    a = simplify_gen_subreg (submode, op0, mode, i * subsize);
  	  else
  	    a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
  				   NULL_RTX, submode, submode, size);
! 	  if (CONSTANT_P (op1) || GET_CODE (op1) == REG)
  	    b = simplify_gen_subreg (submode, op1, mode, i * subsize);
  	  else
  	    b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp,


That doesn't work when submode is smaller than a word.  At register allocation
time, every subreg of a single hard register is assumed to be a low part,
even if its not.

-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330


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