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Re: Vector modes under hppa64-hpu
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: Steve Ellcey <sje at cup dot hp dot com>
- Cc: gcc at gcc dot gnu dot org, dave at hiauly1 dot hia dot nrc dot ca
- Date: Thu, 25 Jul 2002 12:28:03 -0700
- Subject: Re: Vector modes under hppa64-hpu
- References: <200207251554.IAA01229@hpsje.cup.hp.com>
> I got a pass on simd-1.c too. I ran tests on PA32, PA64, and IA64;
> while simd-1.c passed on all of them simd-2 and simd-4 failed on PA32
> (hppa1.1-hp-hpux11.00) with -O2 but passed on PA64 or IA64. On PA32 I
> got:
>
> [hpsje - sje_merge] $ obj_pa_gcc/gcc/cc1 -O2 simd-2.c
> tempf
> simd-2.c: In function `tempf':
> simd-2.c:17: error: unrecognizable insn:
Hi Steve.
It looks like it's Joern's new simd code that's generating your bad
instruction. I have a quick fix for this [untested]. Can you give it
a whirl and run tests?
Aldy
2002-07-25 Aldy Hernandez <aldyh@redhat.com>
* optabs.c (expand_vector_binop): Call simplify_gen_subreg if op
is a register.
Index: optabs.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/optabs.c,v
retrieving revision 1.141
diff -c -p -r1.141 optabs.c
*** optabs.c 22 Jul 2002 14:22:58 -0000 1.141
--- optabs.c 25 Jul 2002 19:13:27 -0000
*************** expand_vector_binop (mode, binoptab, op0
*** 1973,1984 ****
t = NULL_RTX;
else
t = simplify_gen_subreg (submode, target, mode, i * subsize);
! if (CONSTANT_P (op0))
a = simplify_gen_subreg (submode, op0, mode, i * subsize);
else
a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
NULL_RTX, submode, submode, size);
! if (CONSTANT_P (op1))
b = simplify_gen_subreg (submode, op1, mode, i * subsize);
else
b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp,
--- 1973,1984 ----
t = NULL_RTX;
else
t = simplify_gen_subreg (submode, target, mode, i * subsize);
! if (CONSTANT_P (op0) || GET_CODE (op0) == REG)
a = simplify_gen_subreg (submode, op0, mode, i * subsize);
else
a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
NULL_RTX, submode, submode, size);
! if (CONSTANT_P (op1) || GET_CODE (op1) == REG)
b = simplify_gen_subreg (submode, op1, mode, i * subsize);
else
b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp,