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Re: -msse producing sse2 instructions




"Gareth Pearce" <tilps@hotmail.com> writes:

> ----- Original Message -----
> From: "Andreas Jaeger" <aj@suse.de>
> To: "Dylan Cuthbert" <dylan@q-games.com>
> Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
> Sent: Sunday, July 21, 2002 11:28 PM
> Subject: Re: -msse producing sse2 instructions
>
>
>> "Dylan Cuthbert" <dylan@q-games.com> writes:
>>
>> > Hello there, thanks for the quick response.
>> >
>> > Whilst I see if I can track down a small test program (it only occurs in
> the
>> > big unwieldy programs right now, as these things always seem to do)
> here's
>> > some extra info:
>> >
>> > I'm compiling currently
>> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> from
>> > the very latest experimental cygwin distribution.
>>
>>
>> > One of the problems with tracking this down is my machine is an Athlon
> MP
>> > and has no trouble with SSE2 instructions, however a client's machine is
> an
>> > Athlon 4 and exhibits the problem. And of course we need the SSE
> builtins
>> > for speed improvements. -_-;;
>>
>> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
>> SSE only).
>>
>> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
>> Therefore are you sure that you get an Illegal instruction for
>> cvttss2si? Or is this some other error and you're just confused.
>
> please ignore me if i am showing my ignorance ... but I have in the past
> recieved the impression that athlon SSE implementation is not completely
> compatible with intel SSE, and under some circumstances will result in
> illegal instructions. (different athlon revisions have better/worse
> support).

It should be compatible - if not, report it, so that we can verify it
and change GCC so that using SSE on Athlon 4s will do the right thing.
I believe the situation described as having a patch waiting for it in the other fork of this thread sounds very similar to past experience, and is quite probably what I was thinking of.

Gareth


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