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Re: Register Pressure in Instruction Level Parallelism (fwd)
- From: Geoff Keating <geoffk at geoffk dot org>
- To: "Duraid Madina" <duraid at fl dot net dot au>
- Cc: gcc at gcc dot gnu dot org
- Date: 14 Jul 2002 23:24:46 -0700
- Subject: Re: Register Pressure in Instruction Level Parallelism (fwd)
- References: <000701c22ad9$c08e3450$022a17ac@suugaku>
"Duraid Madina" <duraid@fl.net.au> writes:
> Seriously, what are you trying to say here? That GCC is (or should be) a
> compiler that's fast, *particularly* for large or pathological programs?
> I hope not. I think that donning the "GCC shall remain in P-time"
> blinkers is rather inappropriate when it comes to instruction
> scheduling.
Linear, please, or at least n log n. Users often try to compile
programs that have thousands of whatever 'n' is, and we've repeatedly
been bitten by algorithms that were things like
(number of basic blocks)^3.
The last set of complaints about GCC's compilation speed were because
part of the register allocator is, if I remember correctly,
(number of instructions)*(number of register classes)^2
and we significantly increased the number of register classes on x86.
Pathological programs occur more often in applications than you might
think, and they're often the result of an attempt to make some chunk
of code go really fast (and so the user often wants as much
optimisation as possible).
--
- Geoffrey Keating <geoffk@geoffk.org> <geoffk@redhat.com>