Re: generation of divxu opcode

[Peter Barada <pbarada at mail dot wm dot sps dot mot dot com>]

> > upper 8 bits of Rd. Valid results are not assured if division by
> > zero is attempted or an overflow occurs.
>
>"Valid results are not assured."  Nasty.

I wouldn't expect anything valid *could* be generated if the division
either overflows or an attempt to divide by zero is made.  I'll
assume(for the H8 and like the m68k) that either the condition codes
are set or a trap is taken which allows recovery.

Before the m68k had 32x32 multiply/divides, it was quite common to see: 

     divu.w %d1,%d0
     bvc.b L1
     bsr   __divsu
L1:

Which would attempt the divide as a 32/16->16 and if it overflowed,
call the library routine which divided %d1 by %d0 and left the
quotient in the low word of %d0, and the remainder in the high word of
%d0.  If there was no overflow then it branched around the call(since
the registers held the correct values).

Now it the H8 processor trashes Rd if the divide overflows then its a
different story.

-- 
Peter Barada                                   Peter.Barada@motorola.com
Wizard                                         781-852-2768 (direct)
WaveMark Solutions(wholly owned by Motorola)   781-270-0193 (fax)