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Re: generation of divxu opcode
Kai Henningsen writes:
> aph@cambridge.redhat.com (Andrew Haley) wrote on 05.07.02 in <15653.38739.706764.135879@cuddles.cambridge.redhat.com>:
>
> > Dhananjay R. Deshpande writes:
>
> > > >From the H8300 programming manual -
> >
> > > The divxu instruction divides the contents of a 16-bit register Rd
> > > (destination register) by the contents of an 8-bit register Rs
> > > (source register) and stores the result in the 16-bit register
> > > Rd. The division is unsigned. The operation performed is 16 bits
> > > ÷ 8 bits -> 8-bit quotient and 8-bit remainder. The quotient is
> > > placed in the lower 8 bits of Rd. The remainder is placed in the
> > > upper 8 bits of Rd. Valid results are not assured if division by
> > > zero is attempted or an overflow occurs.
> >
> > "Valid results are not assured." Nasty.
>
> Care to explain what you would consider "valid results" in the
> cases in question?
Sure. In the case of an overflow, it would be possible to specify
that the result of the operation is equal to the 8-bit truncation of
the correct result. This wouldn't help for a true division by zero,
but would leave all other results well-defined.
Andrew.