Re: GCC/powerpc AltiVec expectations.

[Kumar Gala <kumar dot gala at motorola dot com>]

> Actually the PIM does:
>
> #pragma altivec_vrsave on | off | allon
> When this pragma is on, the compiler maintains the VRSAVE register. 
> With allon
> selected, the compiler changes the VRSAVE register to have all bits 
> set. It is combined with #pragma altivec_vrsave off by having a parent 
> function do the work once of setting the value of the VRSAVE register 
> with #pragma altivec_vrsave allon and the function it calls uses the 
> setting #pragma altivec_vrsave off.
Does gcc support all three modes? I know pragma's have been frowned on 
typically with regards to gcc.


> The VRSAVE special purpose register (SPR256, named vrsave in assembly
> instructions) is used to inform the operating system which vector 
> registers
> (VRs) need to be saved and reloaded across context switches. Bit n of 
> this
> register is set to 1 if vector register vn needs to be saved and 
> restored
> across a context switch. Otherwise, the operating system may return that
> register with any value that does not violate security after a context 
> switch.
> The most signiÞcant bit in the 32-bit word is bit 0.
We have found that if you use VRSAVE as a bit vector and the context 
switching code is going to check every bit of the vector to determine 
what to save and restore, you might as well not bother and just save all 
VRs and restore all VRs.

If the OS always saves & restores on context switches of AltiVec enabled 
processes then VRSAVE is not required and the extra code needed to 
update it in the users application also goes away.

- kumar