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Re: Alpha CPU-specific builtins
- From: Richard Henderson <rth at redhat dot com>
- To: Falk Hueffner <falk dot hueffner at student dot uni-tuebingen dot de>
- Cc: gcc at gcc dot gnu dot org
- Date: Mon, 3 Jun 2002 10:11:03 -0700
- Subject: Re: Alpha CPU-specific builtins
- References: <87it5cc65d.fsf@student.uni-tuebingen.de> <20020525215942.A28314@redhat.com> <87znynym64.fsf@student.uni-tuebingen.de> <20020526142714.A1836@redhat.com> <87bsaxqw7o.fsf@student.uni-tuebingen.de> <20020530122839.A5344@redhat.com> <87bsatjjs0.fsf@student.uni-tuebingen.de> <20020602194807.C13119@redhat.com> <87vg90iqon.fsf@student.uni-tuebingen.de>
On Mon, Jun 03, 2002 at 12:48:08PM +0200, Falk Hueffner wrote:
> OK, here it is. It contains your zap stuff, works nicely as far as I
> tested.
Ok, obvious fix once I watched it fail. The 'J' constraint
only matches CONST_INT. So we need something else to match
CONST_VECTOR. I chose 'W' since it's next in line ('V' is
used by generic stuff). Patch appended.
Also, I fibbed to you about one of the zap patterns -- the magic
constant is 0xff, not 7. I guess I was thinking ext/ins/mask.
r~
--- alpha.c.orig Mon Jun 3 09:54:31 2002
+++ alpha.c Mon Jun 3 09:54:39 2002
@@ -1675,7 +1675,9 @@
return GET_CODE (value) == HIGH;
case 'U':
return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
-
+ case 'W':
+ return (GET_CODE (value) == CONST_VECTOR
+ && value == CONST0_RTX (GET_MODE (value)));
default:
return false;
}
--- alpha.h.orig Mon Jun 3 09:54:14 2002
+++ alpha.h Mon Jun 3 09:52:25 2002
@@ -795,7 +795,9 @@
'T' is a HIGH.
- 'U' is a symbolic operand. */
+ 'U' is a symbolic operand.
+
+ 'W' is a vector zero. */
#define EXTRA_CONSTRAINT alpha_extra_constraint
--- alpha.md.orig Mon Jun 3 09:54:47 2002
+++ alpha.md Mon Jun 3 09:56:09 2002
@@ -6970,8 +6970,8 @@
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
- (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rJ")
- (match_operand:V8QI 2 "reg_or_0_operand" "rJ")))]
+ (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"minub8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
@@ -6997,8 +6997,8 @@
(define_insn "sminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
- (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rJ")
- (match_operand:V8QI 2 "reg_or_0_operand" "rJ")))]
+ (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"minsb8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
@@ -7078,8 +7078,8 @@
(define_insn "umaxv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
- (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rJ")
- (match_operand:V8QI 2 "reg_or_0_operand" "rJ")))]
+ (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxub8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
@@ -7105,8 +7105,8 @@
(define_insn "smaxv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
- (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rJ")
- (match_operand:V8QI 2 "reg_or_0_operand" "rJ")))]
+ (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxsb8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
@@ -7132,8 +7132,8 @@
(define_insn "umaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
- (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rJ")
- (match_operand:V4HI 2 "reg_or_0_operand" "rJ")))]
+ (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxuw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])
@@ -7159,8 +7159,8 @@
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
- (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rJ")
- (match_operand:V4HI 2 "reg_or_0_operand" "rJ")))]
+ (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxsw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])