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Re: Alpha CPU-specific builtins
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: Falk Hueffner <falk dot hueffner at student dot uni-tuebingen dot de>
- Cc: Richard Henderson <rth at redhat dot com>, gcc at gcc dot gnu dot org
- Date: 03 Jun 2002 11:42:18 +1000
- Subject: Re: Alpha CPU-specific builtins
- References: <87it5cc65d.fsf@student.uni-tuebingen.de> <20020525215942.A28314@redhat.com> <87znynym64.fsf@student.uni-tuebingen.de> <20020526142714.A1836@redhat.com> <87bsaxqw7o.fsf@student.uni-tuebingen.de> <20020530122839.A5344@redhat.com> <87bsatjjs0.fsf@student.uni-tuebingen.de>
>>>>> "Falk" == Falk Hueffner <falk.hueffner@student.uni-tuebingen.de> writes:
> x.c:1: unrecognizable insn:
> (insn 32 13 15 (set (reg:V8QI 2 $2)
> (const_vector:V8QI[
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> (const_int 0 [0x0])
> ] )) -1 (nil)
> (nil))
add a pattern to clear a vector register, probably with an xor.
you'll need one eventually.
see the ppc pattern:
(define_insn "*movv16qi_const0"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(match_operand:V16QI 1 "zero_constant" ""))]
"TARGET_ALTIVEC"
"vxor %0,%0,%0"
[(set_attr "type" "vecsimple")])
ideally though, you should be generating all this from your "movv8qi"
pattern.
...assuming this instruction should be generated in the first place.
aldy