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Re: make sh-1 support in gcc obsolete?


Joern Rennecke wrote:
> 
> Ralf Corsepius wrote:
> [sh-1 is broken and sh-coff was broken]
> > This is sad to hear. I am inclined this qualifies to be a bug in GCC and
> > as a regression to gcc-2.95.x
> 
> Yes.
> 
> > No, this perspective doesn't match. The SH1/sh-coff is among the targets
> > RTEMS supports.
> 
> Are there still people using it, apart from testing that it still works?

Yes but they are still using 2.95.x.
 
> > RTEMS currently is in the process of switching to 3.1 (Still using
> > SH-coff, still supporting the SH1), so we probably will encounter the
> > problems you mention.
> 
> Note that the assembler silently assembles the file as SH-2 code, and
> thus it is linked and run by the simulator as SH-2.  But tests on SH1 hardware
> can be expected to fail.
> If we want to continue to support SH-1, we should have the compiler pass an
> option to the assembler to limit the acceptable instruction set to the one
> being used, so that regressions are caught.  Otherwise, SH-2 instruction are
> just too likely to sneak back in.

OK. I went for ASM_CPU_SPEC in sh.h but this was the closest thing I
could find.

#define ASM_SPEC  "%{ml:-little} %{mrelax:-relax}"

Is this the place that needs to be modified so -m1, etc get translated?

I don't see the option on my sh- assembler that matches.

SH options:
-little                 generate little endian code
-big                    generate big endian code
-relax                  alter jump instructions for long displacements
-small                  align sections to 4 byte boundaries, not 16
-dsp                    enable sh-dsp insns, and disable sh3e / sh4
insns.

-dsp appears to be the closest option but it allows sh2 instructions.

Any ideas?
 
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-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel@OARcorp.com                 On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
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