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Re: SPARC code inefficiency


Jan Hubicka <jh@suse.cz> writes:

  > > 
  > > The source code below comes from md5.c from gnupg. 
  > > The code is compiled with gcc-3.1 -O2 on sparc
  > > (adding -mcpu=v8 or ultrasparc doesn't change much)
  > > 
  > > Look at all the uses for the %o2 register:
  > > 
  > > 32 lines matching "o2" in buffer md5.s.
  > >      11:	add	%fp, -80, %o2
  > >      21:	mov	%o2, %i5
  > >      40:	ld	[%o2], %i0
  > >      53:	add	%o2, 4, %o2
  > >      54:	ld	[%o2], %i0
  > 
  > Hmm, this is exactly kind of code my webizer pass present on the CFG branch
  > solves.  WHat happens is that sequence of things like:
  > 
  > *(a++)=x;
  > *(a++)=x;
  > *(a++)=x;
  > *(a++)=x;
  > 
  > Gets converted into
  > *a=x;
  > a1=a+1;
  > *a1=x;
  > a2=a1+1;
  > and so on.. CSE knows how to optimize this case.

Oh, wait, let's try:  -O2 -fssa
Yep, it works quite nicely, all those adds are gone and the reg+offset
addressing mode is used: 

26 lines matching "ld\\|g1\\|fp" in buffer md5.s.
     10:	add	%fp, -80, %g1
     11:	ld	[%i0], %o3
     13:	ld	[%i0+4], %o7
     15:	ld	[%i0+8], %o1
     16:	mov	%g1, %i3
     17:	ld	[%i0+12], %o2
     20:	ldub	[%i2], %i1
     23:	ldub	[%i2+1], %i0
     25:	ldub	[%i2+2], %i1
     27:	ldub	[%i2+3], %i0
     33:	ld	[%g1], %i0
     46:	ld	[%g1+4], %i0
     59:	ld	[%g1+8], %i0
     72:	ld	[%g1+12], %i0
     85:	ld	[%g1+16], %i1
     98:	ld	[%g1+20], %i1
    111:	ld	[%g1+24], %i1
    124:	ld	[%g1+28], %i1
    137:	ld	[%g1+32], %i1
    150:	ld	[%g1+36], %i1
    163:	ld	[%g1+40], %i1
    176:	ld	[%g1+44], %i1
    189:	ld	[%g1+48], %i1
    202:	ld	[%g1+52], %i1
    215:	ld	[%g1+56], %i1
    228:	ld	[%g1+60], %i1


Now, another thing that can be done is to replace %g1 with %fp-80....

Is your webizer patch more likely to applied and enabled by default
than the SSA code?


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