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Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h?

>  + enum
>>  > + {
>>  > +   SH_DEBUG_INFO_R0 = 0,
>>  > +   SH_DEBUG_INFO_PR = 17,
>>  > +   SH_DEBUG_INFO_GBR = 18,
>> This will break gdb. Register 22 ir SR. What are these registers?
> gcc does not emit debug information for SR - if it was encountered in
> DBX_REGISTER_NUMBER, the compiler would abort.  So we don't actually have a
> number
> allocated in the interface right now, and if we need one, we are free to choose
> any.
>> Doesn't SH have only mach and macl?
> Yes, it has only mach and macl.  But you could hold a 64 bit value in this
> register
> pair, in which case MACH always holds the high part and MACL holds the low part.
> So the idea is to use SH_DEBUG_INFO_MACH_BIG for big endian, and
> SH_DEBUG_INFO_MACH_LITTLE for little endian.  This way, it is clear where low
> and high
> part are.  both SH_DEBUG_INFO_MACH_BIG and SH_DEBUG_INFO_MACH_LITTLE are then
> mapped
> to gdb's MACH.  Note that SH_DEBUG_INFO_MACH_BIG is the old MACH number, and
> SH_DEBUG_INFO_MACL is the old MACL number, so we have full backwards
> compatibility.
> Having both this backwards compatibility and the ability to represent a 64 bit
> value
> in MACH/MACL for little endian was the point of using 22 for

The correct way to represent a 64 bit value in MACH and MACL is to emit 
a location expression indicating that the value is split across the 
MACL/MACH registers.  GDB currently only handles the simple case of this 
(but hey that is just a bug).  If GCC can't emit this info correctly in 
all cases then I guess GCC also has a bug and that bug also needs to be 


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