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Re: Post-register-allocation opportunitistic optimizer?
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: tm at mail dot kloo dot net
- Cc: gcc at gcc dot gnu dot org, joern dot rennecke at superh dot com
- Date: Fri, 03 May 2002 17:23:16 -0400 (EDT)
- Subject: Re: Post-register-allocation opportunitistic optimizer?
- References: <Pine.LNX.firstname.lastname@example.org>
> For example, GCC generates this code for a right shift by 8 on the
> mov.w e0,r2
> mov.b r0h,r0l
> mov.b r2l,r0h
> mov.b r2h,r2l
> exts.w r2
> mov.w r2,e0
I was thinking about the same thing. Shifts that require loops are in
the same situation. Also, if you want to use stw.l for argument push
on H8/S, you need to know what registers are available, but this might
> 3. New optimizer pass which runs after global alloc which
> opportunistically replaces slow sequences with fast sequences if hard
> registers are available.
This sounds very reasonable to me.