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Re: cross target report on gcc 3.1-20020423
> Actually, now that I thought about this some more, I remembered that
> there is another solution. The i960 has the same problem as ia64 here,
> long double is 80 bits, but it has 128 bit size/alignment in memory. We
> can borrow the same solution that was used for ia64, which means
> defining the macro INTEL_EXTENDED_IEEE_FORMAT, plus other changes to
> make this work. With this change, long double will use TFmode instead
> of XFmode, and then objc build problem will go away. I think objc will
> still fail to work because of the overloading of TFmode onto _C_DBL I
> mentioned above, but at least it will build. I vaguely recall Eric
> Christopher working on this patch, because i960 problems showed up
> inside Red Hat when we tried building it once, but I don't recall what
> happened. Maybe he didn't finish writing the patch, or maybe I lost it.
> This patch risks introducing ABI changes if done wrong, and would take
> some time to write and test if we don't already have it.
>
I'm stunned. I actually have an old version of the patch around. Barring
the changes that were required to real.c and real.h (which i think were
already done) at least.
If this is the one you were wanting I can probably bring it up to current
FSF sources, as you can tell, it's quite old :)
-eric
--
A fire drill does not demand
a fire.
Index: configure.in
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/configure.in,v
retrieving revision 1.368.2.5
diff -u -p -w -r1.368.2.5 configure.in
--- configure.in 2000/12/08 21:08:03 1.368.2.5
+++ configure.in 2001/05/21 16:43:09
@@ -1989,14 +1989,17 @@ changequote([,])dnl
i960-*-coff*)
tm_file="${tm_file} dbxcoff.h i960/i960-coff.h libgloss.h"
tmake_file=i960/t-960bare
+ float_format=i386
use_collect2=yes
;;
i960-*-rtems)
tmake_file="i960/t-960bare t-rtems"
tm_file="${tm_file} dbxcoff.h i960/rtems.h"
+ float_format=i386
use_collect2=yes
;;
i960-*-*) # Default i960 environment.
+ float_format=i386
use_collect2=yes
;;
ia64*-*-elf*)
Index: config/i960/i960.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/i960/i960.c,v
retrieving revision 1.53.56.2
diff -u -p -w -r1.53.56.2 i960.c
--- i960.c 2001/03/01 20:38:34 1.53.56.2
+++ i960.c 2001/05/21 16:43:14
@@ -1018,13 +1018,13 @@ i960_output_ldconst (dst, src)
output_asm_insn ("ldconst %1,%0", operands);
return "";
}
- else if (mode == XFmode)
+ else if (mode == TFmode)
{
REAL_VALUE_TYPE d;
long value_long[3];
int i;
- if (fp_literal_zero (src, XFmode))
+ if (fp_literal_zero (src, TFmode))
return "movt 0,%0";
REAL_VALUE_FROM_CONST_DOUBLE (d, src);
@@ -1409,6 +1409,44 @@ i960_function_name_declare (file, name,
}
}
+
+
+/* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
+ through memory plus an extra GR scratch register. Except that you can
+ either get the first from SECONDARY_MEMORY_NEEDED or the second from
+ SECONDARY_RELOAD_CLASS, but not both.
+
+ We got into problems in the first place by allowing a construct like
+ (subreg:TF (reg:TI)), which we got from a union containing a long double.
+ This solution attempts to prevent this situation from ocurring. When
+ we see something like the above, we spill the inner register to memory. */
+
+rtx
+spill_tfmode_operand (in, force)
+ rtx in;
+ int force;
+{
+ if (GET_CODE (in) == SUBREG
+ && GET_MODE (SUBREG_REG (in)) == TImode
+ && GET_CODE (SUBREG_REG (in)) == REG)
+ {
+ rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE);
+ return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
+ }
+ else if (force && GET_CODE (in) == REG)
+ {
+ rtx mem = gen_mem_addressof (in, NULL_TREE);
+ return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
+ }
+ else if (GET_CODE (in) == MEM
+ && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
+ {
+ return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
+ }
+ else
+ return in;
+}
+
/* Compute and return the frame size. */
int
@@ -2423,7 +2461,7 @@ hard_regno_mode_ok (regno, mode)
case DImode: case DFmode:
return (regno & 1) == 0;
- case TImode: case XFmode:
+ case TImode: case TFmode:
return (regno & 3) == 0;
default:
@@ -2434,7 +2472,7 @@ hard_regno_mode_ok (regno, mode)
{
switch (mode)
{
- case SFmode: case DFmode: case XFmode:
+ case SFmode: case DFmode: case TFmode:
case SCmode: case DCmode:
return 1;
@@ -2612,14 +2650,7 @@ i960_arg_size_and_align (mode, type, siz
size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
if (type == 0)
- {
- /* ??? This is a hack to properly correct the alignment of XFmode
- values without affecting anything else. */
- if (size == 3)
- align = 4;
- else
align = size;
- }
else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
align = TYPE_ALIGN (type) / BITS_PER_WORD;
else
@@ -2711,9 +2742,7 @@ i960_output_long_double (file, value)
REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
- fprintf (file,
- "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
- value_long[0], dstr, value_long[1], value_long[2]);
+ fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n", value_long[0], dstr, value_long[1], value_long[2]);
fprintf (file, "\t.word\t0x0\n");
}
Index: config/i960/i960.h
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/i960/i960.h,v
retrieving revision 1.68.24.2
diff -u -p -w -r1.68.24.2 i960.h
--- i960.h 2001/04/18 01:12:46 1.68.24.2
+++ i960.h 2001/05/21 16:43:17
@@ -423,21 +423,13 @@ extern int target_flags;
/* Width in bits of a pointer. See also the macro `Pmode' defined below. */
#define POINTER_SIZE 32
-/* Width in bits of a long double. Define to 96, and let
- ROUND_TYPE_ALIGN adjust the alignment for speed. */
-#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
-
-/* ??? This must be a constant, because real.c and real.h test it with #if. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 96
-
-/* Define this to set long double type size to use in libgcc2.c, which can
- not depend on target_flags. */
-#if defined(__LONG_DOUBLE_64__)
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
-#else
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
-#endif
+/* A C expression for the size in bits of the type `long double' on the target
+ machine. If you don't define this, the default is two words. */
+#define LONG_DOUBLE_TYPE_SIZE 128
+
+/* Tell real.c that this is the 80-bit Intel extended float format
+ packaged in a 128-bit entity. */
+#define INTEL_EXTENDED_IEEE_FORMAT
/* Allocation boundary (in *bits*) for storing pointers in memory. */
#define POINTER_BOUNDARY 32
@@ -481,12 +473,6 @@ extern int target_flags;
? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
: (ALIGN))
-/* Make XFmode floating point quantities be 128 bit aligned. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
- && (ALIGN) < 128 ? 128 : (ALIGN))
-
/* Macros to determine size of aggregates (structures and unions
in C). Normally, these may be defined to simply return the maximum
alignment and simple rounded-up size, but on some machines (like
@@ -590,7 +576,7 @@ extern int target_flags;
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On 80960, the cpu registers can hold any mode but the float registers
- can only hold SFmode, DFmode, or XFmode. */
+ can only hold SFmode, DFmode, or TFmode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
Index: config/i960/i960.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/i960/i960.md,v
retrieving revision 1.42
diff -u -p -w -r1.42 i960.md
--- i960.md 2000/06/01 17:04:21 1.42
+++ i960.md 2001/05/21 16:43:17
@@ -1470,6 +1470,13 @@
"cvtir %1,%0"
[(set_attr "type" "fpcvt")])
+(define_insn "floatsitf2"
+ [(set (match_operand:TF 0 "register_operand" "=d*f")
+ (float:TF (match_operand:SI 1 "register_operand" "d")))]
+ "TARGET_NUMERICS"
+ "cvtir %1,%0"
+ [(set_attr "type" "fpcvt")])
+
;; Convert a float to an actual integer.
;; Truncation is performed as part of the conversion.
;; The i960 requires conversion from DFmode to DImode to make
@@ -1496,6 +1503,13 @@
"cvtzri %1,%0"
[(set_attr "type" "fpcvt")])
+(define_insn "fixunstfsi"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (unsigned_float:TF (match_operand:SI 1 "register_operand" "f")))]
+ "TARGET_NUMERICS"
+ "cvtzri %1,%0"
+ [(set_attr "type" "fpcvt")])
+
(define_expand "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))]
@@ -2036,10 +2050,10 @@
;; Tetra (16 byte) float support.
-(define_expand "cmpxf"
+(define_expand "cmptf"
[(set (reg:CC 36)
- (compare:CC (match_operand:XF 0 "register_operand" "")
- (match_operand:XF 1 "nonmemory_operand" "")))]
+ (compare:CC (match_operand:TF 0 "register_operand" "")
+ (match_operand:TF 1 "nonmemory_operand" "")))]
"TARGET_NUMERICS"
"
{
@@ -2050,27 +2064,27 @@
(define_insn ""
[(set (reg:CC 36)
- (compare:CC (match_operand:XF 0 "register_operand" "f")
- (match_operand:XF 1 "nonmemory_operand" "fGH")))]
+ (compare:CC (match_operand:TF 0 "register_operand" "f")
+ (match_operand:TF 1 "nonmemory_operand" "fGH")))]
"TARGET_NUMERICS"
"cmpr %0,%1"
[(set_attr "type" "fpcc")])
-(define_expand "movxf"
- [(set (match_operand:XF 0 "general_operand" "")
- (match_operand:XF 1 "fpmove_src_operand" ""))]
+(define_expand "movtf"
+ [(set (match_operand:TF 0 "general_operand" "")
+ (match_operand:TF 1 "fpmove_src_operand" ""))]
""
"
{
- if (emit_move_sequence (operands, XFmode))
+ if (emit_move_sequence (operands, TFmode))
DONE;
}")
(define_insn ""
- [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
- (match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
- "register_operand (operands[0], XFmode)
- || register_operand (operands[1], XFmode)"
+ [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m")
+ (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
+ "register_operand (operands[0], TFmode)
+ || register_operand (operands[1], TFmode)"
"*
{
switch (which_alternative)
@@ -2092,9 +2106,9 @@
}"
[(set_attr "type" "move,move,load,fpload,fpstore")])
-(define_insn "extendsfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f,d")
- (float_extend:XF
+(define_insn "extendsftf2"
+ [(set (match_operand:TF 0 "register_operand" "=f,d")
+ (float_extend:TF
(match_operand:SF 1 "register_operand" "d,f")))]
"TARGET_NUMERICS"
"@
@@ -2102,9 +2116,9 @@
movre %1,%0"
[(set_attr "type" "fpmove")])
-(define_insn "extenddfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f,d")
- (float_extend:XF
+(define_insn "extenddftf2"
+ [(set (match_operand:TF 0 "register_operand" "=f,d")
+ (float_extend:TF
(match_operand:DF 1 "register_operand" "d,f")))]
"TARGET_NUMERICS"
"@
@@ -2112,85 +2126,106 @@
movre %1,%0"
[(set_attr "type" "fpmove")])
-(define_insn "truncxfdf2"
+(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "register_operand" "=d")
(float_truncate:DF
- (match_operand:XF 1 "register_operand" "f")))]
+ (match_operand:TF 1 "register_operand" "f")))]
"TARGET_NUMERICS"
"movrl %1,%0"
[(set_attr "type" "fpmove")])
-(define_insn "truncxfsf2"
+(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "register_operand" "=d")
(float_truncate:SF
- (match_operand:XF 1 "register_operand" "f")))]
+ (match_operand:TF 1 "register_operand" "f")))]
"TARGET_NUMERICS"
"movr %1,%0"
[(set_attr "type" "fpmove")])
-(define_insn "floatsixf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (float:XF (match_operand:SI 1 "register_operand" "d")))]
+(define_insn "floatditf2"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (float:TF (match_operand:DI 1 "register_operand" "d")))]
"TARGET_NUMERICS"
"cvtir %1,%0"
[(set_attr "type" "fpcvt")])
-(define_insn "fix_truncxfsi2"
+(define_insn "fix_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
+ (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
"TARGET_NUMERICS"
"cvtzri %1,%0"
[(set_attr "type" "fpcvt")])
-(define_insn "fixuns_truncxfsi2"
+(define_insn "fixuns_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
- (unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
+ (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
+ "TARGET_NUMERICS"
+ "cvtzri %1,%0"
+ [(set_attr "type" "fpcvt")])
+
+(define_insn "fix_trunctfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (fix:DI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
+ "TARGET_NUMERICS"
+ "cvtzri %1,%0"
+ [(set_attr "type" "fpcvt")])
+
+(define_insn "fixuns_trunctfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (unsigned_fix:DI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
+ "TARGET_NUMERICS"
+ "cvtzri %1,%0"
+ [(set_attr "type" "fpcvt")])
+
+(define_insn "fixunstfdi"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (unsigned_float:TF (match_operand:DI 1 "register_operand" "f")))]
"TARGET_NUMERICS"
"cvtzri %1,%0"
[(set_attr "type" "fpcvt")])
-(define_insn "addxf3"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
- (match_operand:XF 2 "nonmemory_operand" "fGH")))]
+(define_insn "addtf3"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fGH")
+ (match_operand:TF 2 "nonmemory_operand" "fGH")))]
"TARGET_NUMERICS"
"addr %1,%2,%0"
[(set_attr "type" "fpadd")])
-(define_insn "subxf3"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
- (match_operand:XF 2 "nonmemory_operand" "fGH")))]
+(define_insn "subtf3"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (minus:TF (match_operand:TF 1 "nonmemory_operand" "fGH")
+ (match_operand:TF 2 "nonmemory_operand" "fGH")))]
"TARGET_NUMERICS"
"subr %2,%1,%0"
[(set_attr "type" "fpadd")])
-(define_insn "mulxf3"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
- (match_operand:XF 2 "nonmemory_operand" "fGH")))]
+(define_insn "multf3"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (mult:TF (match_operand:TF 1 "nonmemory_operand" "%fGH")
+ (match_operand:TF 2 "nonmemory_operand" "fGH")))]
"TARGET_NUMERICS"
"mulr %1,%2,%0"
[(set_attr "type" "fpmul")])
-(define_insn "divxf3"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
- (match_operand:XF 2 "nonmemory_operand" "fGH")))]
+(define_insn "divtf3"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (div:TF (match_operand:TF 1 "nonmemory_operand" "fGH")
+ (match_operand:TF 2 "nonmemory_operand" "fGH")))]
"TARGET_NUMERICS"
"divr %2,%1,%0"
[(set_attr "type" "fpdiv")])
-(define_insn "negxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (neg:XF (match_operand:XF 1 "register_operand" "f")))]
+(define_insn "negtf2"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (neg:TF (match_operand:TF 1 "register_operand" "f")))]
"TARGET_NUMERICS"
"subr %1,0f0.0,%0"
[(set_attr "type" "fpadd")])
-(define_insn "absxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (match_operand:XF 1 "register_operand" "f")))]
+(define_insn "abstf2"
+ [(set (match_operand:TF 0 "register_operand" "=f")
+ (abs:TF (match_operand:TF 1 "register_operand" "f")))]
"(TARGET_NUMERICS)"
"cpysre %1,0f0.0,%0"
[(set_attr "type" "fpmove")])
Index: config/i960/t-960bare
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/i960/t-960bare,v
retrieving revision 1.17
diff -u -p -w -r1.17 t-960bare
--- t-960bare 1999/10/05 08:07:42 1.17
+++ t-960bare 2001/05/21 16:43:17
@@ -21,8 +21,8 @@ xp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define EXTENDED_FLOAT_STUBS' > xp-bit.c
cat $(srcdir)/config/fp-bit.c >> xp-bit.c
-MULTILIB_OPTIONS=mnumerics/msoft-float mlong-double-64
-MULTILIB_DIRNAMES=float soft-float ld64
+MULTILIB_OPTIONS=mnumerics/msoft-float
+MULTILIB_DIRNAMES=float soft-float
MULTILIB_MATCHES=mnumerics=msb mnumerics=msc mnumerics=mkb mnumerics=mkc mnumerics=mmc mnumerics=mcb mnumerics=mcc mnumerics=mjf msoft-float=msa msoft-float=mka msoft-float=mca msoft-float=mcf
LIBGCC = stmp-multilib