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documentation for operand constraints/patterns?
- From: David Mosberger <davidm at napali dot hpl dot hp dot com>
- To: gcc at gcc dot gnu dot org
- Date: Mon, 15 Apr 2002 16:37:06 -0700
- Subject: documentation for operand constraints/patterns?
- Reply-to: davidm at hpl dot hp dot com
Is anybody maintaining documentation for the operand constraints and
patterns available for inline assembly? The reason I'm asking is that
I just had another person fall into the trap of not using the %P
pattern on ia64 when the "m" constraint was used. Such errors are
rather silly and timeconsuming.
If there is no interest in maintaining such a document in general,
would someone at least be interested in doing so for ia64? As a
starting point, I listed the stuff I'm aware of below.
--david
* Operand constraints:
`b' branch register
`c' predicate register ('c' as in "conditional")
`d' application register residing in M-unit
`e' application register residing in I-unit
`f' floating-point register
`r' general register
`m' memory address (must %Pn to get post-increment/decrement!)
`o' offsetable-only memory address (use when post-increment/decrement
cannot be used)
'G' float constant 0.0 or 1.0
`I' 14-bit signed integer constant
`J' 22-bit signed integer constant
`K' 8-bit signed integer constant for logical instructions
`L' 8-bit adjusted signed integer constant for compare pseudo-ops
`M' 6-bit unsigned integer constant for shift counts
`N' 9-bit signed integer constant for load/store post-increments
`O' the constant zero.
`P' 0 or -1 for dep instruction
* Operand printing formats:
C Swap and print a comparison operator.
D Print an FP comparison operator.
E Print 32 - constant, for SImode shifts as extract.
e Print 64 - constant, for DImode rotates.
F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
a floating point register emitted normally.
I Invert a predicate register by adding 1.
J Select the proper predicate register for a condition.
j Select the inverse predicate register for a condition.
O Append .acq for volatile load.
P Postincrement of a MEM.
Q Append .rel for volatile store.
S Shift amount for shladd instruction.
T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
for Intel assembler.
U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
for Intel assembler.
r Print register name, or constant 0 as r0. HP compatibility for
Linux kernel.
+ Print branch-prediction qualifier (.spnt, .dpnt, .sptk, spnt) based
on branch likelihood.
, Print parenthesized predicate of a predicated instruction.