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Re: RTL generation patterns


On Wed, 27 Feb 2002 15:56:47 +0100
Jan Hubicka <jh@suse.cz> wrote:

> > 
> > I fail to understand how the second rtl
> > (store)instrucion is generated from this pattern. how
> > does  
> > (match_operand:SI 0 "general_operand" "") produce
> > (mem/f:SI (plus:SI (reg:SI 28)
> >                 (const_int -16 [0xfffffff0])) 0)
> > shouldnt it only produce a single rtl instruction like
> > only a mem? please comment 
> 
> When optimizing, gcc forces all nontrivial operands to be load to
> registers first in order to asist CSE to do more optimizations.
> Also may be that ARM is simply refusing constant 1 as general_operand
> making gcc code generator to do the move in order to make expander
> math.
> 

Just to check myself:
Isn't 

	mem/f:SI (plus:SI (reg:SI 28)
                 (const_int -16 [0xfffffff0])) 0)

just a simple 'indexed' location like :
	insn -16(Rn), Rm
('insn' content of memory pointed by Rn-16 to Rm) ?

I think, if legitimate_address_p returns true for operands which satisfy:
	GET_CODE(x)==PLUS && REG_P(XEXP(x,0)) && GET_CODE(XEXP(x,1)) == CONST_INT
this is.
Am I wrong?

~d

> Honza
> > 
> > regards,
> > danish
> > 
> > 
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