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Re: RTL generation patterns
- From: Jan Hubicka <jh at suse dot cz>
- To: Danish Samad <danishsamad at yahoo dot com>
- Cc: gcc at gcc dot gnu dot org, durdana at enabtech dot com, syed_rauf_ul_hassan at hotmail dot com
- Date: Wed, 27 Feb 2002 15:56:47 +0100
- Subject: Re: RTL generation patterns
- References: <email@example.com>
> I fail to understand how the second rtl
> (store)instrucion is generated from this pattern. how
> (match_operand:SI 0 "general_operand" "") produce
> (mem/f:SI (plus:SI (reg:SI 28)
> (const_int -16 [0xfffffff0])) 0)
> shouldnt it only produce a single rtl instruction like
> only a mem? please comment
When optimizing, gcc forces all nontrivial operands to be load to
registers first in order to asist CSE to do more optimizations.
Also may be that ARM is simply refusing constant 1 as general_operand
making gcc code generator to do the move in order to make expander
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