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Re: [TESTCASE] Minimized testcase for AltiVec segfault
- From: Daniel Egger <degger at fhm dot edu>
- To: David Edelsohn <dje at watson dot ibm dot com>
- Cc: GCC Developer Mailinglist <gcc at gcc dot gnu dot org>,Aldy Hernandez <aldyh at redhat dot com>
- Date: 26 Feb 2002 19:14:07 +0100
- Subject: Re: [TESTCASE] Minimized testcase for AltiVec segfault
- References: <200202261627.LAA29474@makai.watson.ibm.com>
Am Die, 2002-02-26 um 17.27 schrieb David Edelsohn:
> I believe that you are misinformed about the Altivec instruction
> set. Altivec indexed loads are like PowerPC indexed loads: if rA is zero,
> the effective address is 0+rB, not r0+rB.
Mea culpa, you're absolutely right. I got that impression from debugging
it with gdb which gets it wrong as does objdump:
100004b4: 90 1f 00 30 stw r0,48(r31)
100004b8: 81 3f 00 30 lwz r9,48(r31)
100004bc: 7c 00 48 ce lvx v0,r0,r9
100004c0: 38 00 00 38 li r0,56
The AltiVec PIM does not mention it at all but the PEM does.