This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [TESTCASE] Minimized testcase for AltiVec segfault


>>>>> Daniel Egger writes:

Daniel> lvx %v0,0,%r9       <--- This is an offending line.
Daniel> stvx %v0,0,%r9      <--- This is an offending line.

Daniel> One problem with this marked lines is that there is no direct vector
Daniel> load or vector store with the second argument being 0 to directly
Daniel> address the memory at the pointer in the third argument which gcc seem
Daniel> to assume exists.

	I believe that you are misinformed about the Altivec instruction
set.  Altivec indexed loads are like PowerPC indexed loads: if rA is zero,
the effective address is 0+rB, not r0+rB.

David


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]