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Re: [TESTCASE] Minimized testcase for AltiVec segfault
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Daniel Egger <degger at fhm dot edu>
- Cc: GCC Developer Mailinglist <gcc at gcc dot gnu dot org>, Aldy Hernandez <aldyh at redhat dot com>
- Date: Tue, 26 Feb 2002 11:27:04 -0500
- Subject: Re: [TESTCASE] Minimized testcase for AltiVec segfault
>>>>> Daniel Egger writes:
Daniel> lvx %v0,0,%r9 <--- This is an offending line.
Daniel> stvx %v0,0,%r9 <--- This is an offending line.
Daniel> One problem with this marked lines is that there is no direct vector
Daniel> load or vector store with the second argument being 0 to directly
Daniel> address the memory at the pointer in the third argument which gcc seem
Daniel> to assume exists.
I believe that you are misinformed about the Altivec instruction
set. Altivec indexed loads are like PowerPC indexed loads: if rA is zero,
the effective address is 0+rB, not r0+rB.