This is the mail archive of the
mailing list for the GCC project.
SImode -> DImode optimizations
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: gcc at gcc dot gnu dot org
- Date: Fri, 22 Feb 2002 15:32:38 +1030
- Subject: SImode -> DImode optimizations
What's the correct way to let gcc know that SImode insn patterns
leave the high part of a reg in a known state? eg. powerpc has
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
On PowerPC64, this particular insn is guaranteed to leave the high
32 bits of the reg zero. I'd like to avoid gcc generating
unnecessary zero_extendsidi2 insns. I know this can be done by
writing appropriate patterns that combine both operations and emit
a single rlwinm machine insn, but that leaves the zero_extend in
the rtl. What I'm after is a way of zapping the zero_extend, so
is optimized into one insn in the same way as is done for
Or do I have to write a bunch of 3 insn combiners?
Hmm, or something different, like specifying the output of rotlsi3
and other similar instructions is really DImode? If so, how to
do this without breaking things horribly?
IBM OzLabs - Linux Technology Centre