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Re: Conditional call instruction


> 
> 
> --On Wednesday, February 13, 2002 04:38:11 PM +0000 Richard Earnshaw 
> <rearnsha@arm.com> wrote:
> 
> >> Do any of GCC's currently supported targets have a predicated call
> >> instruction that GCC will use when appropriate?  Roughly speaking,
> >> this is an instruction that calls only if some condition is true,
> >> and otherwise falls through.
> >
> > Yes, the ARM has, but with the exception of the obsolete apcs-26 mode
> > (only useful for very early ARM chips) the call will smash the
> > condition-code register.  So a predicated call can only be used when it
> > is  known that the condition code register won't be live afterwards.
> 
> But is sounds like, from Philip's mail, that GCC isn't smart enough
> to use this feature.  Is that corret?

Basically, yes; I can't find a way of describing to the cond-exec code the 
fact that the condition can be used in the instruction but will be 
clobbered afterwards.  Currently if the predicate register is clobbered 
anywhere in the insn the code will abandon all attempts to conditionalize 
a sequence.

Of course, the code could be changed so that gcc would try to re-arrange 
the instructions such that the clobbering insn was moved to the end of the 
sequence, then we could make the call-insn predicable.

Note, the ARM port still has a back-end predicating hook that runs as part 
of final-prescan.  This can conditionalize an insn sequence that ends will 
a call.  If we could make the mid-end code work with a call insn the the 
code in the back-end could be ripped out.

R.



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