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[kjelde@mips.com: Re: SNaN & QNaN on mips]


It seems that the current gcc still does it wrong for mips.


H.J.
----- Forwarded message from Kjeld Borch Egevang <kjelde@mips.com> -----

Delivered-To: hjl@lucon.org
Date: Mon, 4 Feb 2002 07:59:06 +0100 (CET)
From: Kjeld Borch Egevang <kjelde@mips.com>
To: Zhang Fuxin <fxzhang@ict.ac.cn>
Cc: "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: Re: SNaN & QNaN on mips
Precedence: bulk

On Mon, 4 Feb 2002, Zhang Fuxin wrote:

> hi,
> 
> Gcc (2.96 20000731,H.J.LU's rh port for mips) think 0x7fc00000 is QNaN and 
> optimize 0.0/0.0 as 0x7fc00000 for single precision ops,while for my cpu
> (maybe most mips cpu) is a SNaN. R4k user's manual and "See Mips Run" both
>  say so.And experiments confirm this.

MIPS interprets Signalling NaN's different than e.g. Intel. According to 
IEEE754 it _is_ a matter of interpretation. 0x7fc00000 is an SNaN while 
0x7fbfffff is an QNaN. It would be great if you could fix it.

/Kjeld

> Should we correct it?
> 
> >
> >Regards
> >            Zhang Fuxin
> >            fxzhang@ict.ac.cn
> 
> Regards
>             Zhang Fuxin
>             fxzhang@ict.ac.cn
> 

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