condition codes, haifa-sched and virtual-stack-vars

[Greg McGary <greg at mcgary dot org>]

I have a GCC port to a custom RISC that uses condition codes in an
explicit register (doesn't use cc0).  GCC generates bogus code when
expanding an inline.  One of the inline's args is the address of an
automatic, so it is passed to the inline as a move from
virtual-stack-vars to a pseudo.  Later, there's a conditional branch
on bitfield test that expands as bitfield-extract (shift + and),
comparison wtih zero, and branch.  All harmless so far.

Haifa-sched schedules the move from virtual-stack-vars between the
bitfield test sequence and the branch.  Later, global-reg alloc
instantiates virtual-stack-vars as an offset from FP, so the move
mutates into an add of fp+offset, clobbering the condition codes
computed earlier in the bitfield test.

One idea for a localized bandaid is to make the machine-description
wrap moves from virtual-stack-vars in a parallel that has a clobber
CC_REGNUM.  Another idea is to manipulate scheduling parameters so
that haifa doesn't schedule anything between CC set and CC use.
(I haven't yet looked at if/how this can be done.)

What's a better way to fix it?

Thanks,
Greg