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Re: Best options for 64-bit FP on athlon?
- From: Tim Prince <tprince at computer dot org>
- To: Brad Lucier <lucier at math dot purdue dot edu>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 10 Jan 2002 20:25:14 -0800
- Subject: Re: Best options for 64-bit FP on athlon?
- References: <200201102338.g0ANcgT19554@banach.math.purdue.edu>
Brad Lucier wrote:
> I have a lot of FP code where the algorithms depend on setting the precision
> to 64-bits (i.e., no extended precision) for correctness. Since I've
> heard great things on the mail lists about MMX/SSE/SSE2/... doing
> 64-bit FP faster, I want to try it.
>
> But reading the 3.1 docs, I cannot figure out what options to give to
> get what I want. Now, maybe I missed something, but I don't think
> it's there.
>
> Brad
>
>
Maybe not, but gcc docs don't typically go into hardware to the extent
which appears to be needed here. We don't know of any Athlon supporting
SSE2, which is the only one of those architecture variants which
supports 64-bit FP.
gcc doesn't currently support the parallel paired double instructions
with auto-vectorization, which is the way the most impressive
performance would be obtained with SSE2. The options to generate scalar
SSE2 are -msse2 -march=pentiumpro.
The option -msse doesn't generally work for P-III, but it may work for
Athlon. It uses both mmx and sse (32-bit floating point) without taking
into account that they use the same register territory on a P-III.
--
Tim Prince
tprince@computer.org