Re: writing custom machine descriptions

[Alan Lehotsky <apl at alum dot mit dot edu>]

I haven't looked at what the Itanium port does (it faces some of this sort of thing in dealing with
bundles of instructions - they may have some useful mechanisms to assist in generating code.

The other port to look at is the Analog Devices ADI 2106x port - the SHARC chip has 48 bit instructions
which can do multiple ALU operations and memory read/writes in parallel in a single instruction - there
are modifications to the peephole pass that allow it to pack these multiple operations into a single instruction
(it's pretty simpleminded, but it works fairly well).

You can get a copy of the port from the analog devices web site - its buried somewhere on their ftp  (ftp.adi.com if
I remember - but it's been a long time....)  I did a lot of work on this port for Mercury Computer, but you'd have to
talk to them about getting my changes/improvements.

Or you might hire me as a consultant to work in this....

At 4:40 AM -0800 12/27/01, Danish Samad wrote:
>
>hello,
>
>Our processor is based on VLIW(very large instruction
>word) architecture. It is capable of executing five
>instructions in one cylce. For such an architecture
>will I have to simply write machine description and
>configuration files? or will I have to update\modify
>the gcc backend? Considering the fact we have to
>generare optimized parallel assembly.
>
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