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126.gcc broken as of Dec15
- From: Diego Novillo <dnovillo at redhat dot com>
- To: Jan Hubicka <jh at suse dot cz>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 20 Dec 2001 17:05:36 -0500
- Subject: 126.gcc broken as of Dec15
- Organization: Red Hat Canada
Jan,
This patch seems to have broken 126.gcc in SPEC95. It's a
runtime error triggered by -O3. The resulting 126.gcc binary
fails to compile c-decl-s.i.
I still haven't chased the bug, but reverting this patch fixes
the regression. Both trunk and the cfg-branch are broken.
Diego.
Fri Dec 14 21:23:54 CET 2001 Jan Hubicka <jh@suse.cz>
* config.gcc: Revamp target_cpu_default2 to strings;
support new x86 variants.
* i386.c (override_options): Default x86_cpu_string and x86_arch_string
properly; set prefetch_sse.
* i386.h (x86_prefetch_sse): Declare.
(TARGET_PREFETCH_SSE): New.
(CPP_CPU_DEFAULT_SPEC): Define according to the new macros.
(TARGET_CPU_DEFAULT_*): New.
diff -r -dup ./config.gcc ../../gcc.20011215/gcc/config.gcc
--- ./config.gcc Thu Dec 13 18:14:44 2001
+++ ../../gcc.20011215/gcc/config.gcc Fri Dec 14 15:43:41 2001
@@ -519,6 +519,23 @@ alpha*-*-vxworks*)
use_collect2=yes
thread_file='vxworks'
;;
+alpha64-dec-*vms*)
+ xm_defines=POSIX
+ tm_file="alpha/vms.h alpha/vms64.h"
+ xm_file="alpha/xm-vms.h alpha/xm-vms64.h"
+ tmake_file="alpha/t-alpha alpha/t-vms alpha/t-vms64 alpha/t-ieee"
+ xmake_file=alpha/x-vms
+ exeext=.exe
+ # This removes the cpu type and manufacturer components and
+ # replaces "." with "_" in the operating system version.
+ case $host in *-*-*vms*)
+ target_alias=`echo $host \
+ | sed 's/.*-.*-\(.*\)$/\1/' | sed 's/\./_/g'`
+ ;;
+ esac
+ prefix=/gnu
+ local_prefix=/gnu
+ ;;
alpha*-dec-*vms*)
xm_defines=POSIX
tm_file=alpha/vms.h
@@ -3290,27 +3307,54 @@ esac
target_cpu_default2=
case $machine in
i486-*-*)
- target_cpu_default2=1
+ target_cpu_default2=TARGET_CPU_DEFAULT_i486
;;
i586-*-*)
case $target_alias in
+ k6_2-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_k6_2
+ ;;
+ k6_3-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_k6_3
+ ;;
k6-*)
- target_cpu_default2=4
+ target_cpu_default2=TARGET_CPU_DEFAULT_k6
+ ;;
+ pentium_mmx-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentium_mmx
;;
*)
- target_cpu_default2=2
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentium
;;
esac
;;
i686-*-* | i786-*-*)
case $target_alias in
- athlon-*)
- target_cpu_default2=5
+ athlon_xp-*|athlon_mp-*|athlon_4-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_athlon_sse
+ ;;
+ athlon_tbird-*|athlon-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_athlon
+ ;;
+ pentium2-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentium2
+ ;;
+ pentium3-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentium3
+ ;;
+ pentium4-*)
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentium4
;;
*)
- target_cpu_default2=3
+ target_cpu_default2=TARGET_CPU_DEFAULT_pentiumpro
;;
esac
+ ;;
+x86_64-*-*)
+ # We should have hammer chip here, but it does not exist yet and
+ # thus it is not supported. Athlon_SSE is probably equivalent feature
+ # wise to hammer from our point of view except for 64bit mode.
+ target_cpu_default2=TARGET_CPU_DEFAULT_athlon_sse
;;
alpha*-*-*)
case $machine in
diff -r -dup ./config/i386/i386.c ../../gcc.20011215/gcc/config/i386/i386.c
--- ./config/i386/i386.c Thu Dec 13 06:34:08 2001
+++ ../../gcc.20011215/gcc/config/i386/i386.c Fri Dec 14 15:27:04 2001
@@ -81,6 +81,8 @@ struct processor_costs size_cost = { /*
{3, 3, 3}, /* cost of storing SSE registers
in SImode, DImode and TImode */
3, /* MMX or SSE register to integer */
+ 0, /* size of prefetch block */
+ 0, /* number of parallel prefetches */
};
/* Processor costs (relative to an add) */
static const
@@ -116,6 +118,8 @@ struct processor_costs i386_cost = { /*
{4, 8, 16}, /* cost of storing SSE registers
in SImode, DImode and TImode */
3, /* MMX or SSE register to integer */
+ 0, /* size of prefetch block */
+ 0, /* number of parallel prefetches */
};
static const
@@ -150,7 +154,9 @@ struct processor_costs i486_cost = { /*
in SImode, DImode and TImode */
{4, 8, 16}, /* cost of storing SSE registers
in SImode, DImode and TImode */
- 3 /* MMX or SSE register to integer */
+ 3, /* MMX or SSE register to integer */
+ 0, /* size of prefetch block */
+ 0, /* number of parallel prefetches */
};
static const
@@ -185,7 +191,9 @@ struct processor_costs pentium_cost = {
in SImode, DImode and TImode */
{4, 8, 16}, /* cost of storing SSE registers
in SImode, DImode and TImode */
- 3 /* MMX or SSE register to integer */
+ 3, /* MMX or SSE register to integer */
+ 0, /* size of prefetch block */
+ 0, /* number of parallel prefetches */
};
static const
@@ -220,7 +228,9 @@ struct processor_costs pentiumpro_cost =
in SImode, DImode and TImode */
{2, 2, 8}, /* cost of storing SSE registers
in SImode, DImode and TImode */
- 3 /* MMX or SSE register to integer */
+ 3, /* MMX or SSE register to integer */
+ 32, /* size of prefetch block */
+ 6, /* number of parallel prefetches */
};
static const
@@ -255,7 +265,9 @@ struct processor_costs k6_cost = {
in SImode, DImode and TImode */
{2, 2, 8}, /* cost of storing SSE registers
in SImode, DImode and TImode */
- 6 /* MMX or SSE register to integer */
+ 6, /* MMX or SSE register to integer */
+ 32, /* size of prefetch block */
+ 1, /* number of parallel prefetches */
};
static const
@@ -290,7 +302,9 @@ struct processor_costs athlon_cost = {
in SImode, DImode and TImode */
{2, 2, 8}, /* cost of storing SSE registers
in SImode, DImode and TImode */
- 6 /* MMX or SSE register to integer */
+ 6, /* MMX or SSE register to integer */
+ 64, /* size of prefetch block */
+ 6, /* number of parallel prefetches */
};
static const
@@ -326,6 +340,8 @@ struct processor_costs pentium4_cost = {
{2, 2, 8}, /* cost of storing SSE registers
in SImode, DImode and TImode */
10, /* MMX or SSE register to integer */
+ 64, /* size of prefetch block */
+ 6, /* number of parallel prefetches */
};
const struct processor_costs *ix86_cost = &pentium_cost;
@@ -578,16 +594,23 @@ enum cmodel ix86_cmodel;
/* which cpu are we scheduling for */
enum processor_type ix86_cpu;
+/* which unit we are generating floating point math for */
+enum fpmath_unit ix86_fpmath;
+
/* which instruction set architecture to use. */
int ix86_arch;
/* Strings to hold which cpu and instruction set architecture to use. */
const char *ix86_cpu_string; /* for -mcpu=<xxx> */
const char *ix86_arch_string; /* for -march=<xxx> */
+const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
/* # of registers to use to pass arguments. */
const char *ix86_regparm_string;
+/* true if sse prefetch instruction is not NOOP. */
+int x86_prefetch_sse;
+
/* ix86_regparm_string as a number */
int ix86_regparm;
@@ -813,6 +836,7 @@ override_options ()
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0, 1}
};
+ static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
static struct pta
{
const char *const name; /* processor name or nickname. */
@@ -822,7 +846,7 @@ override_options ()
PTA_SSE = 1,
PTA_SSE2 = 2,
PTA_MMX = 4,
- PTA_SSEPREFETCH = 8,
+ PTA_PREFETCH_SSE = 8,
PTA_3DNOW = 16,
PTA_3DNOW_A = 64
} flags;
@@ -837,21 +861,21 @@ override_options ()
{"i686", PROCESSOR_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
{"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
- {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSEPREFETCH},
+ {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
{"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 |
- PTA_MMX | PTA_SSEPREFETCH},
+ PTA_MMX | PTA_PREFETCH_SSE},
{"k6", PROCESSOR_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
- {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
+ {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A},
- {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH
+ {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
| PTA_3DNOW | PTA_3DNOW_A},
- {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
+ {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
- {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
+ {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
- {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
+ {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
};
@@ -861,8 +885,12 @@ override_options ()
SUBTARGET_OVERRIDE_OPTIONS;
#endif
- ix86_arch = PROCESSOR_I386;
- ix86_cpu = (enum processor_type) TARGET_CPU_DEFAULT;
+ if (!ix86_cpu_string && ix86_arch_string)
+ ix86_cpu_string = ix86_arch_string;
+ if (!ix86_cpu_string)
+ ix86_cpu_string = cpu_names [TARGET_CPU_DEFAULT];
+ if (!ix86_arch_string)
+ ix86_arch_string = TARGET_64BIT ? "athlon-4" : "i386";
if (ix86_cmodel_string != 0)
{
@@ -896,47 +924,45 @@ override_options ()
sorry ("%i-bit mode not compiled in",
(target_flags & MASK_64BIT) ? 64 : 32);
- if (ix86_arch_string != 0)
- {
- for (i = 0; i < pta_size; i++)
- if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
- {
- ix86_arch = processor_alias_table[i].processor;
- /* Default cpu tuning to the architecture. */
- ix86_cpu = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
- && !(target_flags & MASK_MMX_SET))
- target_flags |= MASK_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
- && !(target_flags & MASK_3DNOW_SET))
- target_flags |= MASK_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
- && !(target_flags & MASK_3DNOW_A_SET))
- target_flags |= MASK_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
- && !(target_flags & MASK_SSE_SET))
- target_flags |= MASK_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
- && !(target_flags & MASK_SSE2_SET))
- target_flags |= MASK_SSE2;
- break;
- }
+ for (i = 0; i < pta_size; i++)
+ if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
+ {
+ ix86_arch = processor_alias_table[i].processor;
+ /* Default cpu tuning to the architecture. */
+ ix86_cpu = ix86_arch;
+ if (processor_alias_table[i].flags & PTA_MMX
+ && !(target_flags & MASK_MMX_SET))
+ target_flags |= MASK_MMX;
+ if (processor_alias_table[i].flags & PTA_3DNOW
+ && !(target_flags & MASK_3DNOW_SET))
+ target_flags |= MASK_3DNOW;
+ if (processor_alias_table[i].flags & PTA_3DNOW_A
+ && !(target_flags & MASK_3DNOW_A_SET))
+ target_flags |= MASK_3DNOW_A;
+ if (processor_alias_table[i].flags & PTA_SSE
+ && !(target_flags & MASK_SSE_SET))
+ target_flags |= MASK_SSE;
+ if (processor_alias_table[i].flags & PTA_SSE2
+ && !(target_flags & MASK_SSE2_SET))
+ target_flags |= MASK_SSE2;
+ if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
+ x86_prefetch_sse = true;
+ break;
+ }
- if (i == pta_size)
- error ("bad value (%s) for -march= switch", ix86_arch_string);
- }
+ if (i == pta_size)
+ error ("bad value (%s) for -march= switch", ix86_arch_string);
- if (ix86_cpu_string != 0)
- {
- for (i = 0; i < pta_size; i++)
- if (! strcmp (ix86_cpu_string, processor_alias_table[i].name))
- {
- ix86_cpu = processor_alias_table[i].processor;
- break;
- }
- if (i == pta_size)
- error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
- }
+ for (i = 0; i < pta_size; i++)
+ if (! strcmp (ix86_cpu_string, processor_alias_table[i].name))
+ {
+ ix86_cpu = processor_alias_table[i].processor;
+ break;
+ }
+ if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
+ x86_prefetch_sse = true;
+ if (i == pta_size)
+ error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
if (optimize_size)
ix86_cost = &size_cost;
@@ -1066,8 +1092,45 @@ override_options ()
if (TARGET_RTD)
error ("-mrtd calling convention not supported in the 64bit mode");
/* Enable by default the SSE and MMX builtins. */
- target_flags |= MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE;
+ target_flags |= (MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE);
+ ix86_fpmath = FPMATH_SSE;
}
+ else
+ ix86_fpmath = FPMATH_387;
+
+ if (ix86_fpmath_string != 0)
+ {
+ if (! strcmp (ix86_fpmath_string, "387"))
+ ix86_fpmath = FPMATH_387;
+ else if (! strcmp (ix86_fpmath_string, "sse"))
+ {
+ if (!TARGET_SSE)
+ {
+ warning ("SSE instruction set disabled, using 387 arithmetics");
+ ix86_fpmath = FPMATH_387;
+ }
+ else
+ ix86_fpmath = FPMATH_SSE;
+ }
+ else if (! strcmp (ix86_fpmath_string, "387,sse")
+ || ! strcmp (ix86_fpmath_string, "sse,387"))
+ {
+ if (!TARGET_SSE)
+ {
+ warning ("SSE instruction set disabled, using 387 arithmetics");
+ ix86_fpmath = FPMATH_387;
+ }
+ else if (!TARGET_80387)
+ {
+ warning ("387 instruction set disabled, using SSE arithmetics");
+ ix86_fpmath = FPMATH_SSE;
+ }
+ else
+ ix86_fpmath = FPMATH_SSE | FPMATH_387;
+ }
+ else
+ error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
+ }
/* It makes no sense to ask for just SSE builtins, so MMX is also turned
on by -msse. */
@@ -8117,8 +8180,8 @@ ix86_expand_fp_movcc (operands)
/* For SF/DFmode conditional moves based on comparisons
in same mode, we may want to use SSE min/max instructions. */
- if (((TARGET_SSE && GET_MODE (operands[0]) == SFmode)
- || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))
+ if (((TARGET_SSE_MATH && GET_MODE (operands[0]) == SFmode)
+ || (TARGET_SSE2 && TARGET_SSE_MATH && GET_MODE (operands[0]) == DFmode))
&& GET_MODE (ix86_compare_op0) == GET_MODE (operands[0])
/* The SSE comparisons does not support the LTGT/UNEQ pair. */
&& (!TARGET_IEEE_FP
@@ -11816,22 +11879,13 @@ ix86_expand_builtin (exp, target, subtar
return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3, arglist, target);
case IX86_BUILTIN_PREFETCH_3DNOW:
- icode = CODE_FOR_prefetch_3dnow;
- arg0 = TREE_VALUE (arglist);
- op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
- mode0 = insn_data[icode].operand[0].mode;
- pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
- if (! pat)
- return NULL_RTX;
- emit_insn (pat);
- return NULL_RTX;
-
case IX86_BUILTIN_PREFETCHW:
- icode = CODE_FOR_prefetchw;
+ icode = CODE_FOR_prefetch_3dnow;
arg0 = TREE_VALUE (arglist);
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ op1 = (fcode == IX86_BUILTIN_PREFETCH_3DNOW ? const0_rtx : const1_rtx);
mode0 = insn_data[icode].operand[0].mode;
- pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
+ pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0), op1);
if (! pat)
return NULL_RTX;
emit_insn (pat);
diff -r -dup ./config/i386/i386.h ../../gcc.20011215/gcc/config/i386/i386.h
--- ./config/i386/i386.h Thu Dec 13 06:34:10 2001
+++ ../../gcc.20011215/gcc/config/i386/i386.h Fri Dec 14 15:27:05 2001
@@ -86,6 +86,9 @@ struct processor_costs {
in SImode, DImode and TImode*/
const int mmxsse_to_integer; /* cost of moving mmxsse register to
integer and vice versa. */
+ const int prefetch_block; /* bytes moved to cache for prefetch. */
+ const int simultaneous_prefetches; /* number of parallel prefetch
+ operations. */
};
extern const struct processor_costs *ix86_cost;
@@ -224,6 +227,7 @@ extern const int x86_add_esp_4, x86_add_
extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
extern const int x86_epilogue_using_move, x86_decompose_lea;
+extern int x86_prefetch_sse;
#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
@@ -262,6 +266,7 @@ extern const int x86_epilogue_using_move
#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
+#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
@@ -272,7 +277,9 @@ extern const int x86_epilogue_using_move
#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
-#define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
+#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
+#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
+ && (ix86_fpmath & FPMATH_387))
#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
@@ -365,10 +372,6 @@ extern const int x86_epilogue_using_move
{ "no-sse2", -MASK_SSE2, N_("") }, \
{ "no-sse2", MASK_SSE2_SET, \
N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
- { "mix-sse-i387", MASK_MIX_SSE_I387, \
- N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
- { "no-mix-sse-i387", -MASK_MIX_SSE_I387, \
- N_("Do not use both SSE and i387 instruction sets for floating point arithmetics") },\
{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
N_("sizeof(long double) is 16") }, \
{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
@@ -404,8 +407,14 @@ enum processor_type
PROCESSOR_PENTIUM4,
PROCESSOR_max
};
+enum fpmath_unit
+{
+ FPMATH_387 = 1,
+ FPMATH_SSE = 2
+};
extern enum processor_type ix86_cpu;
+extern enum fpmath_unit ix86_fpmath;
extern int ix86_arch;
@@ -421,6 +430,8 @@ extern int ix86_arch;
#define TARGET_OPTIONS \
{ { "cpu=", &ix86_cpu_string, \
N_("Schedule code for given CPU")}, \
+ { "fpmath=", &ix86_fpmath_string, \
+ N_("Generate floating point mathematics using given instruction set")},\
{ "arch=", &ix86_arch_string, \
N_("Generate code for given CPU")}, \
{ "regparm=", &ix86_regparm_string, \
@@ -474,24 +485,61 @@ extern int ix86_arch;
%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
#endif
+#define TARGET_CPU_DEFAULT_i386 0
+#define TARGET_CPU_DEFAULT_i486 1
+#define TARGET_CPU_DEFAULT_pentium 2
+#define TARGET_CPU_DEFAULT_pentiumpro 3
+#define TARGET_CPU_DEFAULT_pentium2 4
+#define TARGET_CPU_DEFAULT_pentium3 5
+#define TARGET_CPU_DEFAULT_pentium4 6
+#define TARGET_CPU_DEFAULT_k6 7
+#define TARGET_CPU_DEFAULT_k6_2 8
+#define TARGET_CPU_DEFAULT_k6_3 9
+#define TARGET_CPU_DEFAULT_athlon 10
+#define TARGET_CPU_DEFAULT_athlon_sse 11
+
+#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
+ "pentiumpro", "pentium2", "pentium3", \
+ "pentium4", "k6", "k6-2", "k6-3",\
+ "athlon", "athlon-4"}
#ifndef CPP_CPU_DEFAULT_SPEC
-#if TARGET_CPU_DEFAULT == 1
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
#endif
-#if TARGET_CPU_DEFAULT == 2
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
#endif
-#if TARGET_CPU_DEFAULT == 3
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
#endif
-#if TARGET_CPU_DEFAULT == 4
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
+-D__tune_pentium2__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
+-D__tune_pentium2__ -D__tune_pentium3__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
#endif
-#if TARGET_CPU_DEFAULT == 5
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
#endif
-#if TARGET_CPU_DEFAULT == 6
-#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
+#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
#endif
#ifndef CPP_CPU_DEFAULT_SPEC
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
@@ -525,30 +573,45 @@ extern int ix86_arch;
%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
%{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
+%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
+ -D__pentium__mmx__ \
+ %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
-D__pentiumpro -D__pentiumpro__ \
%{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
-%{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
+%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
+ %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
+%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
+ %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
+%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
+ %{!mcpu*:-D__tune_athlon__ }}\
+%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
+ -D__athlon_sse__ \
+ %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
%{m386|mcpu=i386:-D__tune_i386__ }\
%{m486|mcpu=i486:-D__tune_i486__ }\
%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
-%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__\
+%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
-D__tune_pentiumpro__ }\
%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
-D__tune_athlon__ }\
+%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
+-D__tune_athlon_sse__ }\
%{mcpu=pentium4:-D__tune_pentium4__ }\
%{march=march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
-D__SSE__ }\
%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
-%{march=k6|march=k6-2|march=k6-3\
+%{march=k6-2|march=k6-3\
march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
|march=athlon-mp: -D__3dNOW__ }\
-%{mcpu=mcpu=pentium4: -D__SSE2__ }\
+%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
+|march=athlon-mp: -D__3dNOW_A__ }\
+%{march=mcpu=pentium4: -D__SSE2__ }\
%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
#ifndef CPP_CPU_SPEC
@@ -1271,7 +1334,7 @@ enum reg_class
#define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
#define SSE_FLOAT_MODE_P(m) \
- ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
+ ((TARGET_SSE_MATH && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
#define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
#define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
@@ -2255,6 +2318,12 @@ while (0)
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
+/* Number of bytes moved into a data cache for a single prefetch operation. */
+#define PREFETCH_BLOCK ix86_cost->prefetch_block
+
+/* Number of prefetch operations that can be done in parallel. */
+#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
+
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
#define MOVE_MAX 16
@@ -3112,6 +3181,7 @@ extern enum cmodel ix86_cmodel;
/* Variables in i386.c */
extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
extern const char *ix86_arch_string; /* for -march=<xxx> */
+extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
extern const char *ix86_regparm_string; /* # registers to use to pass args */
extern const char *ix86_align_loops_string; /* power of two alignment for loops */
extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
diff -r -dup ./config/i386/i386.md ../../gcc.20011215/gcc/config/i386/i386.md
--- ./config/i386/i386.md Mon Dec 10 09:30:11 2001
+++ ../../gcc.20011215/gcc/config/i386/i386.md Fri Dec 14 15:27:05 2001
@@ -93,8 +93,6 @@
;; 44 This is a `sfence' operation.
;; 45 This is a noop to prevent excessive combiner cleverness.
;; 46 This is a `femms' operation.
-;; 47 This is a `prefetch' (3DNow) operation.
-;; 48 This is a `prefetchw' operation.
;; 49 This is a 'pavgusb' operation.
;; 50 This is a `pfrcp' operation.
;; 51 This is a `pfrcpit1' operation.
@@ -2776,7 +2774,7 @@
(match_operand:SF 1 "register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
- "reload_completed || !TARGET_SSE2"
+ "reload_completed || !TARGET_SSE"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
@@ -6890,14 +6888,14 @@
[(set (match_operand:DF 0 "register_operand" "")
(plus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "addsf3"
[(set (match_operand:SF 0 "register_operand" "")
(plus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Subtract instructions
@@ -7207,14 +7205,14 @@
[(set (match_operand:DF 0 "register_operand" "")
(minus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "subsf3"
[(set (match_operand:SF 0 "register_operand" "")
(minus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Multiply instructions
@@ -7533,14 +7531,14 @@
[(set (match_operand:DF 0 "register_operand" "")
(mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "")
(mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Divide instructions
@@ -7587,14 +7585,14 @@
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
(div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Remainder instructions.
@@ -13849,12 +13847,26 @@
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
+(define_insn "*fop_sf_comm_nosse"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "register_operand" "%0")
+ (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "SF")])
+
(define_insn "*fop_sf_comm"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0,0")
(match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
- "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
+ "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
@@ -13870,17 +13882,31 @@
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+ "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
+(define_insn "*fop_df_comm_nosse"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "register_operand" "%0")
+ (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
+
(define_insn "*fop_df_comm"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0,0")
(match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
- "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
+ "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
@@ -13896,7 +13922,7 @@
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
- "TARGET_SSE2
+ "TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
@@ -13929,12 +13955,30 @@
(const_string "fop")))
(set_attr "mode" "XF")])
+(define_insn "*fop_sf_1_nosse"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:SF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "SF")])
+
(define_insn "*fop_sf_1"
[(set (match_operand:SF 0 "register_operand" "=f,f,x")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
- "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
+ "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
@@ -13954,7 +13998,7 @@
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE
+ "TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
@@ -13966,7 +14010,7 @@
(match_operator:SF 3 "binary_fp_operator"
[(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:SF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
+ "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
@@ -13984,7 +14028,7 @@
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0,0")
(float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
+ "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
@@ -13997,12 +14041,31 @@
(set_attr "ppro_uops" "many")
(set_attr "mode" "SI")])
+(define_insn "*fop_df_1_nosse"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:DF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:DF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
+
+
(define_insn "*fop_df_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
- "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
+ "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
@@ -14022,7 +14085,7 @@
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
- "TARGET_SSE
+ "TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")])
@@ -14033,7 +14096,7 @@
(match_operator:DF 3 "binary_fp_operator"
[(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:DF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
+ "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
@@ -14051,7 +14114,7 @@
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,0")
(float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
+ "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
@@ -14087,7 +14150,7 @@
[(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
- "TARGET_80387 && !TARGET_SSE2"
+ "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
@@ -14381,9 +14444,9 @@
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
- "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
+ "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
{
- if (!TARGET_SSE)
+ if (!TARGET_SSE_MATH)
operands[1] = force_reg (SFmode, operands[1]);
})
@@ -14391,7 +14454,7 @@
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
- && (TARGET_SSE && TARGET_MIX_SSE_I387)"
+ && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
sqrtss\t{%1, %0|%0, %1}"
@@ -14402,7 +14465,7 @@
(define_insn "sqrtsf2_1_sse_only"
[(set (match_operand:SF 0 "register_operand" "=x")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+ "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")
@@ -14412,7 +14475,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
- && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
+ && !TARGET_SSE_MATH"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")
@@ -14421,9 +14484,10 @@
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
- "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
+ "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
+ || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
- if (!TARGET_SSE2)
+ if (!TARGET_SSE2 || !TARGET_SSE_MATH)
operands[1] = force_reg (DFmode, operands[1]);
})
@@ -14431,7 +14495,7 @@
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
- && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
+ && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
sqrtsd\t{%1, %0|%0, %1}"
@@ -14442,7 +14506,7 @@
(define_insn "sqrtdf2_1_sse_only"
[(set (match_operand:DF 0 "register_operand" "=Y")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
- "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+ "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
@@ -14452,7 +14516,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
- && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
+ && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
@@ -14462,7 +14526,8 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
@@ -15963,7 +16028,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
- "TARGET_SSE2"
+ "TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(define_insn "*mindf"
@@ -15973,7 +16038,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
- "TARGET_SSE2 && TARGET_IEEE_FP"
+ "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
"#")
(define_insn "*mindf_nonieee"
@@ -15983,7 +16048,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
- "TARGET_SSE2 && !TARGET_IEEE_FP"
+ "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
"#")
(define_split
@@ -16031,7 +16096,7 @@
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
- "TARGET_SSE2 && reload_completed"
+ "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
"minsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
@@ -16124,7 +16189,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
- "TARGET_SSE2"
+ "TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(define_insn "*maxdf"
@@ -16134,7 +16199,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
- "TARGET_SSE2 && TARGET_IEEE_FP"
+ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
"#")
(define_insn "*maxdf_nonieee"
@@ -16144,7 +16209,7 @@
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
- "TARGET_SSE2 && !TARGET_IEEE_FP"
+ "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
"#")
(define_split
@@ -16191,7 +16256,7 @@
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
- "TARGET_SSE2 && reload_completed"
+ "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
"maxsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
@@ -19333,10 +19398,58 @@
[(set_attr "type" "sse")
(set_attr "memory" "unknown")])
+(define_expand "prefetch"
+ [(prefetch (match_operand:SI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_PREFETCH_SSE || TARGET_3DNOW"
+ "
+{
+ int rw = INTVAL (operands[1]);
+ int locality = INTVAL (operands[2]);
+ if (rw != 0 && rw != 1)
+ abort ();
+ if (locality < 0 || locality > 3)
+ abort ();
+ /* Use 3dNOW prefetch in case we are asking for write prefetch not
+ suported by SSE counterpart or the SSE prefetch is not available
+ (K6 machines). Otherwise use SSE prefetch as it allows specifying
+ of locality. */
+ if (TARGET_3DNOW
+ && (!TARGET_PREFETCH_SSE || rw))
+ {
+ emit_insn (gen_prefetch_3dnow (operands[0], operands[1]));
+ }
+ else
+ {
+ int i;
+ switch (locality)
+ {
+ case 0: /* No temporal locality. */
+ i = 0;
+ break;
+ case 1: /* Lowest level of temporal locality. */
+ i = 3;
+ break;
+ case 2: /* Moderate level of temporal locality. */
+ i = 2;
+ break;
+ case 3: /* Highest level of temporal locality. */
+ i = 1;
+ break;
+ default:
+ abort (); /* We already checked for valid values above. */
+ break;
+ }
+ emit_insn (gen_prefetch_sse (operands[0], GEN_INT (i)));
+ }
+ DONE;
+}")
+
(define_insn "prefetch_sse"
[(unspec [(match_operand:SI 0 "address_operand" "p")
(match_operand:SI 1 "immediate_operand" "n")] 35)]
- "TARGET_SSE || TARGET_3DNOW_A"
+ "TARGET_PREFETCH_SSE"
{
switch (INTVAL (operands[1]))
{
@@ -19512,15 +19625,16 @@
[(set_attr "type" "mmx")])
(define_insn "prefetch_3dnow"
- [(unspec [(match_operand:SI 0 "address_operand" "p")] 47)]
- "TARGET_3DNOW"
- "prefetch\\t%a0"
- [(set_attr "type" "mmx")])
-
-(define_insn "prefetchw"
- [(unspec [(match_operand:SI 0 "address_operand" "p")] 48)]
+ [(prefetch (match_operand:SI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (const_int 0))]
"TARGET_3DNOW"
- "prefetchw\\t%a0"
+{
+ if (INTVAL (operands[1]) == 0)
+ return "prefetch\t%a0";
+ else
+ return "prefetchw\t%a0";
+}
[(set_attr "type" "mmx")])
(define_insn "pf2id"