Re: powerpc & unaligned block moves with fp registers

[David Edelsohn <dje at watson dot ibm dot com>]

>>>>> degger  writes:

Daniel> Ok, I take my "on any cost" back. -Os is of course a different picture,
Daniel> when optimising for size alignment doesn't play such a big role. Anyway
Daniel> the mentioned cases are pretty rare (at least I haven't seen much
Daniel> wrongly aligned structures here in the past) and thusly I also think
Daniel> that aligning them properly would make such a big different in code
Daniel> size.

	Splitting DImode into SImode *probably* will not have much effect.
But choosing lswi versus expanding into byte, half-word, and word loads is
a bigger question.  If you really want to avoid any misaligned accesses,
you need to do the latter.  The natural alignment comes at a cost, for
example, I-cache pressure.  Performance measurements on PowerPC do not
always show an advantage for using more instructions with natural
alignment accesses.  Optimizing for size is not the only case requiring
more consideration.  A real system has a finite cache with a non-zero
delay. 

David