This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

Re: MODES_TIEABLE_P question wrote:
> On Thu, Nov 08, 2001 at 03:28:02PM -0800, Stephen Clarke wrote:
> >   HARD_REGNO_MODE_OK (fpreg, DImode) is 0
> > because fp regs can't hold more than 32 bits.
> This is false reasoning.  HARD_REGNO_MODE_OK may be true
> if HARD_REGNO_NREGS yields 2.

Good!  After pondering a little more since yesterday, I was hoping
this was the case.

But I'm still not totally happy, because I need to hold DImode values
in even/odd pairs of fp registers, so then
  HARD_REGNO_MODE_OK (fr0, SImode) is 1
  HARD_REGNO_MODE_OK (fr0, DImode) is 1
  HARD_REGNO_MODE_OK (fr1, SImode) is 1
  HARD_REGNO_MODE_OK (fr1, DImode) is 0

which would appear to cause a problem if SImode and DImode are

But looking at the code in combine_regs(), if two pseudos are
combined then the combined quantity is given the wider mode,
and will then only be allocated to a register that accepts the wider

This means that tied SImode/DImode pseudos are allocated
to a register that can accept DImode values, and it so happens that
for my target, any register that can accept DImode can also
accept SImode ... maybe this is what is meant by "some other
mechanism ensures the accessibility of the value in a narrower mode"?

Stephen Clarke, Principal Engineer, SuperH Inc.
Phone:1-408-922-4062, Fax:1-408-954-8507,
Mail:  SuperH Inc., 3801 Zanker Rd., San Jose, CA 95134, USA.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]