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Re: PSRLQ question.



to follw up myself, I believe bug is with the program. the line :

	__asm__ __volatile__ ("psrlq %0, %%mm0" : : "X" (shift) );

has "X" which says any type can be used while, according to intel data
scheets

	PSRLQ MEM REG           << OKAY.
	PSRLQ REG REG           << WRONG.

so replacing "X" above with "m" seems to fix the problem.

> t1.s:	psrlq 8(%ebp), %mm0
> t2.s:	psrlq %eax, %mm0

gcc 3.0.2 seems to be doing some more agresstive optimization (?) than
gcc so it is why it would not show up...

[root@pepsi mpeg2enc]# diff -u test.s test-m.s
--- test.s	Sat Nov  3 12:54:29 2001
+++ test-m.s	Sat Nov  3 12:54:19 2001
@@ -22,9 +22,8 @@
 shift_blk:
 	pushl	%ebp
 	movl	%esp, %ebp
-	movl	8(%ebp), %eax
 #APP
-	psrlq %eax, %mm0
+	psrlq 8(%ebp), %mm0
 #NO_APP
 	popl	%ebp
 	ret
[root@pepsi mpeg2enc]#

-- 
Adam
http://www.eax.com	The Supreme Headquarters of the 32 bit registers


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