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Re: powerpc & unaligned block moves with fp registers
- To: David Edelsohn <dje at watson dot ibm dot com>
- Subject: Re: powerpc & unaligned block moves with fp registers
- From: Dale Johannesen <dalej at apple dot com>
- Date: Fri, 2 Nov 2001 11:20:54 -0800
- Cc: Dale Johannesen <dalej at apple dot com>, DJ Delorie <dj at redhat dot com>, gcc at gcc dot gnu dot org
On Friday, November 2, 2001, at 10:56 AM, David Edelsohn wrote:
>>>>>> DJ Delorie writes:
>
>>>> Sigh. DJ wants 3, not 2. That's what PPC chips support in hardware,
>>>> right?
>>>
>>> Not quite; as David pointed you will get an exception if the fetch
>>> crosses a page boundary. Most of the time you won't.
>
> DJ> Oh, right. Makes sense to me now. Thanks!
>
> The PowerPC Book I says that an alignment exception only occurs if
> an FP load or store is not word-aligned. I am pretty sure that my
> research OS sometimes hit an exception beyond just a page fault, but maybe
> it was not an alignment exception.
Book II and III give somewhat more information, but it's not completely
clear. Book III lists some other conditions besides non-word alignment
that
can cause an FP load/store to take an alignment exception (which that
book calls "alignment interrupt".) Book II lists performance in this
case as "poor", which generally means an exception happens, although
"poor" isn't so defined near this particular table.
Overall, it looks like you might get an exception when the fetch crosses a
page boundary, and do so with high probability, but then again you might
not. If DJ must avoid all exceptions he does want 2.