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Re: powerpc & unaligned block moves with fp registers
- To: dje at watson dot ibm dot com
- Subject: Re: powerpc & unaligned block moves with fp registers
- From: DJ Delorie <dj at redhat dot com>
- Date: Fri, 2 Nov 2001 13:59:03 -0500
- CC: gcc at gcc dot gnu dot org, dj at redhat dot com
- References: <200111021557.KAA22830@makai.watson.ibm.com>
> Please submit a revised patch.
2001-11-02 DJ Delorie <dj@redhat.com>
* config/rs6000/rs6000.c (rs6000_emit_move): Make sure that
using FP registers for DImode mem-mem moves is acceptable.
Index: gcc/config/rs6000/rs6000.c
===================================================================
RCS file: gcc/config/rs6000/rs6000.c,v
retrieving revision 1.223
diff -p -3 -r1.223 rs6000.c
*** gcc/config/rs6000/rs6000.c 2001/10/29 21:29:29 1.223
--- gcc/config/rs6000/rs6000.c 2001/11/02 18:47:15
*************** rs6000_emit_move (dest, source, mode)
*** 1805,1810 ****
--- 1805,1832 ----
|| (CONST_DOUBLE_HIGH (operands[1]) == -1
&& CONST_DOUBLE_LOW (operands[1]) < 0)))
abort ();
+
+ if (GET_CODE (operands[0]) == MEM
+ && GET_CODE (operands[1]) == MEM
+ && mode == DImode
+ && ! TARGET_POWERPC64)
+ {
+ /* GCC is setting up a block move. If we let it, it will use FP
+ registers for faster access. We must make sure this is
+ acceptable. */
+ if(SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[0]))
+ || SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[1])))
+ {
+ rtx reg1, reg2;
+ reg1 = gen_reg_rtx(SImode);
+ reg2 = gen_reg_rtx(SImode);
+ rs6000_emit_move (reg1, simplify_subreg (SImode, operands[1], DImode, 0), SImode);
+ rs6000_emit_move (reg2, simplify_subreg (SImode, operands[1], DImode, 4), SImode);
+ rs6000_emit_move (simplify_subreg (SImode, operands[0], DImode, 0), reg1, SImode);
+ rs6000_emit_move (simplify_subreg (SImode, operands[0], DImode, 4), reg2, SImode);
+ return;
+ }
+ }
if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
operands[1] = force_reg (mode, operands[1]);