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Re: powerpc & unaligned block moves with fp registers
- To: Dale Johannesen <dalej at apple dot com>
- Subject: Re: powerpc & unaligned block moves with fp registers
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Thu, 01 Nov 2001 17:51:19 -0500
- cc: DJ Delorie <dj at redhat dot com>, gcc at gcc dot gnu dot org
>>>>> Dale Johannesen writes:
Dale> Yes. I'd recommend using 32 rather than 64 as the alignment cutoff
Dale> in DJ Delorie's patch; a 32-bit-aligned lfd/stfd does not trap.[*]
Dale> [*] at least, on the 750/7400/7450; I haven't gone back farther.
Not even crossing a page boundary?
I still agree that 32-bit alignment should be the cut-off. Page
crossing exceptions should be rare.
Dale> It is true that multiple int load/stores will have the problems you say
Dale> (particularly if not perfectly aligned), but it's hard to believe those
Dale> will be larger than taking the exception. It's true we haven't measured
IBM has measured this when tuning its compilers for its latest