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powerpc & unaligned block moves with fp registers
- To: gcc at gcc dot gnu dot org
- Subject: powerpc & unaligned block moves with fp registers
- From: DJ Delorie <dj at redhat dot com>
- Date: Thu, 1 Nov 2001 14:55:15 -0500
- CC: dj at redhat dot com
Ok, I'm working on this patch, and what it does is pretty specific so
it's hard to pick a suitable name for the command line option to
enable it. I mean, using "-no-using-fp-registers-for-unaligned-block-moves"
just isn't going to work. So, I have two questions:
1. Do we *ever* want to use fp regs for unaligned mem-mem moves? Is
there any 32-bit PPC chip where an unaligned 64-bit fp move is
faster than two (maybe unaligned, maybe mot) 32-bit moves?
2. If we need an option, what should we call it, and what should it
default to?
diff -c3r /uberbuild/src/gcc/config/rs6000/rs6000.c ./config/rs6000/rs6000.c
*** /uberbuild/src/gcc/config/rs6000/rs6000.c Wed Oct 31 05:03:17 2001
--- ./config/rs6000/rs6000.c Wed Oct 31 23:18:50 2001
***************
*** 1805,1810 ****
--- 1805,1830 ----
|| (CONST_DOUBLE_HIGH (operands[1]) == -1
&& CONST_DOUBLE_LOW (operands[1]) < 0)))
abort ();
+
+ #ifdef TARGET_FP_STRICT_ALIGN
+ if (GET_CODE (operands[0]) == MEM
+ && GET_CODE (operands[1]) == MEM
+ && mode == DImode
+ && (MEM_ALIGN(operands[0]) < 8*8
+ || MEM_ALIGN(operands[1]) < 8*8)
+ && TARGET_FP_STRICT_ALIGN
+ && ! TARGET_POWERPC64)
+ {
+ rtx reg1, reg2;
+ reg1 = gen_reg_rtx(SImode);
+ reg2 = gen_reg_rtx(SImode);
+ rs6000_emit_move (reg1, simplify_subreg (SImode, operands[1], DImode, 0), SImode);
+ rs6000_emit_move (reg2, simplify_subreg (SImode, operands[1], DImode, 4), SImode);
+ rs6000_emit_move (simplify_subreg (SImode, operands[0], DImode, 0), reg1, SImode);
+ rs6000_emit_move (simplify_subreg (SImode, operands[0], DImode, 4), reg2, SImode);
+ return;
+ }
+ #endif
if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
operands[1] = force_reg (mode, operands[1]);